Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
1998-05-22
2002-01-01
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S690000, C257S676000
Reexamination Certificate
active
06335564
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor packaging, and more particularly to a single paddle having a semiconductor device and a passive component spaced apart from the semiconductor device and mounted within the single paddle.
2. Description of Related Art
The electronics industry has continued to make significant advances in microelectronics technology. These advances are producing silicon-based integrated circuits with increased circuit density and a corresponding rise in the rate at which functions are performed. However, as circuit density and speed are improved, corresponding progress must also be made in the structures that carry the device and that provide the input/output (I/O) interconnections for the device.
The structure that carries a semiconductor device and provides the necessary I/O interconnections is generally referred to as the package. A typical microelectronic package is designed to provide structure to support and protect the device, and to distribute circuit-generated heat. Furthermore, the package provides connections for signal lines leading into and out of the device, connections that present varying potentials for power and ground, and a wiring structure for I/O signal interconnections within a system. These connections must be made at each level of the packaging hierarchy and as this hierarchy is traversed (i.e., from the chip to the I/O components), connection scaling must be provided because the circuits and connections (i.e., wire lines) continue to increase in size. At the first level of the hierarchy (i.e., chip to substrate), this scaling is usually provided by the leadframe.
A plan view of a conventional leadframe
20
is shown in
FIG. 1 and a
cross-sectional view of leadframe
20
taken along lines
2
—
2
of
FIG. 1
is presented in FIG.
2
. Leadframe
20
has a leadframe body
22
that contains a die-mounting structure
24
. Die-mounting structure
24
is typically formed through an etching or stamping process, and leadframe
20
is usually made of a metal, such as copper (Cu) or a metal alloy.
Die-mounting structure
24
has a square die-pad or paddle
26
for receiving a semiconductor chip
28
that may be adhesively or metallurgically bonded thereon, and four structural supports
30
,
32
,
34
,
36
. Each of the structural supports
30
,
32
,
34
,
36
extends from a corner of paddle
26
to mechanically connect panel
26
to leadframe body
22
.
Die-mounting structure
24
also has numerous leads
38
,
40
that provide scaled connections from chip
28
to the next level of the package. Leads
38
,
40
are commonly connected to chip
28
using a process known as wire bonding. This process consists of attaching flexible wires
42
,
44
between chip bonding pads
46
,
48
and lead posts
50
,
52
, or alternatively, between chip bonding pads
46
,
48
and paddle
26
.
Currently, 25% to 40% of the leads are assigned to different ground and power supply nets. Therefore, power supply and ground contacts contribute substantially to package cost, size, and performance. Furthermore, path inductance from the chip to the outside of the package, which is directly proportional to the path length from the bond pads of the chip to the bond pads of the leads, may negatively impact chip performance, especially for digital/mixed signal and Radio Frequency (RF) chips. While a leadframe based package with a low inductive path is currently available in a deep down-set paddle package, only a single low inductive path is provided and is typically used for ground.
An additional packaging limitation is the inability to effectively integrate passive components that are necessary for proper operation of a semiconductor device. Currently, these components are integrally formed as a part of the semiconductor device are formed and packaged as independent units as shown in FIG.
3
and FIG.
4
.
Referring to FIG.
3
and
FIG. 4
, a semiconductor package
300
of the prior art is shown that utilizes a first paddle area
302
for a semiconductor device
304
and a second paddle area
306
for an off-chip component
308
(e.g., an inductor, capacitor, transformer, etc.). Semiconductor device
304
is connected to off-chip component
308
through leads
310
,
312
that are structurally supported with an adhesive tape. This configuration, however, increases overall package size and path inductance between off-chip component
308
and semiconductor device
304
since the conductive path that forms the electrical connection includes: the distance between device
304
and leads
310
,
312
; the length of leads
310
,
312
; and the distance between leads
310
,
312
and component
308
. Even if the distance between off-chip component
308
and semiconductor device
304
is optimized by including the component as a part of the semiconductor device (i.e, on-board the chip), limits are still encountered that impede optimal performance.
For example, on-chip inductors are usually limited to low Q values (i.e., typically less than 5). Furthermore, on-chip inductors tend to couple noise through the substrate and formation at the substrate requires a thick metal layer (i.e., usually greater than 2 microns) which consumes a significant area of the chip. This reduces chip yield while increasing chip cost. As inductors with values ranging from 1.5 nH to 15 nH and having a Q value greater than 20 are used in somponents such as Voltage Controlled Oscillators (VCO), input and output matching of Low Noise Amplifiers (LNA), output matching RF circuit mixers, and gain adjustment circuits, effective integration into a microelectronic package is highly desirable.
In view of the foregoing, it is an object of the present invention to provide a semiconductor package that incorporates passive electronic components used by a semiconductor device while reducing path inductance and minimizing any increase in the overall size of the package. Additional advantages and features of the present invention will become apparent from the subsequent description and claims taken in conjunction with the accompanying drawings.
SUMMARY OF THE INVENTION
A semiconductor package is provided that includes a paddle and a semiconductor device mounted on the paddle. A passive electronic component is also mounted on the paddle and spaced apart from the semiconductor device. Interconnects provide a conductive path from a bonding pad of the semiconductor device to a bonding pad of the passive electronic component such that the passive electronic component and semiconductor device are operatively connected.
A method of forming a semiconductor package is also provided that includes identifying a paddle region within a leadframe and mounting a semiconductor device within the paddle region. A passive electronic component is selected for use by the semiconductor device and the passive electronic device is mounted spatially apart from the semiconductor device and within the paddle region.
Additional advantages and features of the present invention will become apparent from the subsequent description and claims taken in conjunction with the accompanying drawings.
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patent: 5103283 (1992-04-01), Hite
patent: 5294897 (1994-03-01), Notani et al.
patent: 5428245 (1995-06-01), Lin et al.
patent: 5442228 (1995-08-01), Pham et al.
patent: 5504370 (1996-04-01), Lin et al.
patent: 6034423 (2000-03-01), Mostafazadeh et al.
patent: WO 96 08842 (1996-03-01), None
Patent Abstracts of Japan, vol. 096, No. 004, Apr. 30, 1996 & JP 07 321069 A (NEC Corp.) Dec. 8, 1995.
Patent Abstracts of Japan, vol. 015, No. 405, Oct. 16, 1991 & JP 03 166756 A (Seiko Epson Corp.) Jul. 18, 1991.
Patent Abstracts of Japan, vol. 018, No. 617, Nov. 24, 1994 & JP 06 236959 A (Ibiden Co. Ltd.) Aug. 23, 1994.
Walter Marton, Ansgar Pottbäcker, “Coil in Leadframe,” IEEE Workshop on Chip Package Co-Design CPD '98, ETH Zurich, Switzerland, Mar. 24, 1998.
Conexant Systems Inc.
Potter Roy
Snell & Wilmer L.L.P.
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