Single merging bit DC-suppressed run length limited coding

Details Single merging bit DC-suppressed run length limited coding Single merging bit DC-suppressed run length limited coding

1996-04-05

1998-06-30

Williams, Howard L.

Coded data generation or conversion

Digital code to digital code converters

To or from nrz codes

341 59, H03M 506

Patent

active

057740780

ABSTRACT:
The information to be recorded is divided into 8-bit long data words. Each data word is then converted to 14-bit long code word. The code words are sequentially connected with a one-bit merging bit inserted between the code words to define a code bit sequence. The run-length of 0s in the code bit sequence is limited to be between 2 and 11. The one-bit merging bit normally takes a bit value of 0, but is changed to 1 when any one of the T.sub.min control or T.sub.max control is applied so as to accomplish the run-length limitation. The T.sub.min control is applied when the adjacent bits on both sides of the merging bit are 1s. The T.sub.max control is applied when trailing P bits of a code word preceding the merging bit and leading Q bits of a code word following the merging bit are all 0s, provided that P+Q.gtoreq.11, and in this case, at least either one of the P bits and Q bits has a bit sequence of (00000), and the bit sequence (00000) is changed to (00100).

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