Single mask process for fabricating CMOS structure

Details Single mask process for fabricating CMOS structure Single mask process for fabricating CMOS structure

1983-10-06

1985-04-09

Roy, Upendra

Metal treatment

Compositions

Heat treating

29571, 29576B, 29578, 148187, 357 42, 357 91, H01L 21265, H01L 2126, H01L 754

Patent

active

045099910

ABSTRACT:
A process for forming self-aligned complementary n.sup.+ and p.sup.+ source/drain regions in CMOS structures using a single resist pattern as a mask to form both the n.sup.+ channel implant and then the p.sup.+ channel implant. The resist pattern is formed using conventional lithography techniques to form an implant mask which covers the p.sup.+ channel region while the n.sup.+ source and drain regions are ion implanted. The resist mask is then used as a lift-off mask in order to cover the n.sup.+ channel region while the p.sup.+ source and drain regions are ion implanted.

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Bassous et al., IBM-TDB, 25, (Dec. 1982), 3353.

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