Stock material or miscellaneous articles – Structurally defined web or sheet – Including aperture
Reexamination Certificate
2000-03-06
2004-11-02
Watkins, III, William P. (Department: 1772)
Stock material or miscellaneous articles
Structurally defined web or sheet
Including aperture
C428S137000, C428S156000, C428S167000, C428S209000, C428S457000, C216S041000, C216S047000, C216S002000, C216S024000, C216S079000, C216S099000, C216S046000, C385S088000, C385S049000, C385S014000, C385S065000, C385S083000, C385S137000, C029S464000
Reexamination Certificate
active
06811853
ABSTRACT:
RELATED APPLICATIONS
The present invention was previously described in abandoned provisional patent application 60/118,011 filed Feb. 1, 1999, which is hereby incorporated by reference.
FIELD OF THE INVENTION
The present invention relates generally to methods for making optical, mechanical and electrical micromachined devices. More particularly, the present invention relates to making devices having different feature types (e.g. etched pits, grooves, metal pads) that are accurately located using a single masking step.
BACKGROUND OF THE INVENTION
Micromachined silicon chips are often used for aligning and packaging microoptical components. The silicon chip may have grooves, pits and other etched features that hold fibers, ball lenses, filters or active electrooptical devices. Also, the silicon chip may have metal pads for locating electrooptic devices. For proper operation, microoptical components must be located with high accuracy. Typically, such components must be located with a tolerance more accurate than 1 micron. In order for microoptical components to be located with such high accuracy on a silicon chip, the silicon chip must have features (e.g. grooves, pits, bumps, metal pads, edges) that are located with equal or higher accuracy.
Different features on a silicon chip are typically made using different etching and deposition techniques. For example, V-grooves are made using anisotropic chemical etches and high-aspect ratio trenches with vertical sidewalls are made using directional dry etching techniques such as reactive ion etching. The same single mask cannot be used for both processes because chemical etching will occur in areas to be dry-etched, and dry etching will occur in areas to be chemically etched. A different mask must be applied for each etching technique. This presents a problem in manufacturing certain microoptical devices because aligning a new mask to a feature present on a wafer is time-consuming and relatively inaccurate. If a new mask is applied for every kind of feature to be rendered in the wafer, the features will not be accurately located with respect to one another. This ultimately produces poor alignment tolerance between microoptical components in a microoptical device.
What is needed is a method for manufacturing many different kinds of mechanical features on a wafer using a single masking step so that the features are accurately located.
U.S. Pat. No. 4,863,560 to Hawkins discloses a method for forming different anisotropically etched features in a silicon substrate using several different masks. Alignment and masking steps are not required between etching steps. However, the method of Hawkins does require that successive masks are aligned to one another, and this is a source of misalignment. Masks cannot be aligned accurately to one another to meet the alignment tolerances required of microoptical devices.
U.S. Pat. No. 5,738,757 to Burns et al. discloses a method for multi-depth silicon etching where the mask has many layers of different materials such as silicon dioxide and silicon nitride. The masking layers are removed one at a time, and the different regions of the wafer are exposed to etch at different steps in the manufacturing process. Areas of the wafer exposed at the beginning of the process are etched deeply; areas exposed late in the process are etched only slightly. A disadvantage of the method of Burns et al. is that different etching techniques cannot be totally isolated to different etched regions on the wafer. According to the method of Burns et al., once a region is exposed, there is no way to re-mask it so that it is not affected by subsequent etching steps.
U.S. Pat. No. 4,692,998 to Armstrong et al. discloses a single mask technique for making PIN diodes and similar semiconductor devices.
U.S. Pat. No. 4,004,341 to Tung discloses a method for making high-speed field effect transistors where a trench structure is defined by chromium band that acts as a mask. The method of Tung cannot be used to make a wide variety of micromechanical structures using different etch techniques.
U.S. Pat. No. 4,810,557 to Blonder discloses a method for making a groove in <100> silicon that has a wide portion and a narrow portion. Blonder uses two masking layers to selectively expose the wide portion before exposing the narrow portion, which requires less etching time. In a final step, both wide and narrow portions are exposed and the entire groove is completed in the same etching step. The method of Blonder cannot be used with dissimilar etching techniques and cannot be used to accurately locate a V-groove with respect to features etched by other techniques, or to metallization patterns.
There is a need in the art of micromachining and microoptical device manufacturing for a method of making a variety of mechanical and electrical features on a substrate using a single masking step. This will assure that features are accurately aligned to one another.
OBJECTS AND ADVANTAGES OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide a method for making micromachined devices that:
1) uses a single masking step to locate different mechanical and electrical features and fiducial features;
2) is compatible with silicon micromachining;
3) can be used to make a variety of micromachined optical, electrical, and mechanical devices.
These and other objects and advantages will be apparent upon reading the following description and accompanying drawings.
SUMMARY OF THE INVENTION
These objects and advantages are attained by the present method for fabricating accurately located etched features on a semiconductor substrate. In a first step, a semiconductor substrate with a dielectric layer on a top surface is provided. Then, a patterned metal layer is formed on the dielectric layer. The patterned metal layer can be made using conventional lift-off techniques or masking and etching. Then, a patterned resist layer is formed on the dielectric layer and patterned metal layer. The resist layer is patterned so that edges of the resist are located on top of the metal patterns. This assures that of the dielectric are exposed and areas of the patterned metal layer are exposed. Next, areas of the dielectric not covered by the resist or metal are etched away (e.g. by a dry etch process). Then, exposed areas of the semiconductor substrate are etched. The etched areas of the semiconductor substrate are accurately aligned with respect to the original metal pattern.
Preferably, the semiconductor substrate is made of silicon, but it can also be made of GaAs, germanium or other etchable semiconductors. Anisotropically etchable semiconductors are preferred. Preferably, the dielectric layer is silicon dioxide, but other dielectric layers such as silicon nitride and silicon carbide can also be used.
The patterned metal layer can be made of chromium, gold, titanium, platinum, aluminum, silver, nickel, tungsten, copper or tantalum. Chromium is particularly preferred. Also, the patterned metal layer can comprise several layered metals. Examples include an adhesion layer (titanium or tungsten), a diffusion barrier (nickel or platinum) and a contact layer (gold).
The dielectric layer is preferably etched using dry directional etching such as reactive ion etching. Other suitable directional dry etching techniques are known. Also, the dielectric layer can be etched using wet etches such as fluoride-based wet etches.
The semiconductor substrate can be etched using anisotropic wet etching techniques or dry etching techniques.
In a preferred embodiment, the patterned metal layer comprises a ring shape that encloses the area to be etched. The patterned resist layer does not cover the interior of the ring in this embodiment.
The present invention also includes embodiments where the process is repeated for different regions on the semiconductor substrate. Each region etched is defined by the metal pattern. Between process steps, the resist layer should be removed and reapplied. Alternatively, resist is removed from selected areas and not reapplied.
Al
Sherrer David W.
TenEyck Gregory A.
Baskin Jonathan D.
Shipley Company L.L.C.
Watkins III William P.
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