Single level gate nonvolatile memory device and method for acces

Details Single level gate nonvolatile memory device and method for acces Single level gate nonvolatile memory device and method for acces

1997-05-09

1999-04-06

Hoang, Huan

Static information storage and retrieval

Floating gate

3651851, 36518518, 257371, G11C 1604

Patent

active

058927093

ABSTRACT:
A single level gate NVM device (10) includes p-channel and n-channel floating gate FETs (12, 14), an erasing capacitor (26), and a programming capacitor (28). The NVM device (10) is programmed by applying a programming voltage to the programming capacitor (28) and applying a ground voltage to the sources of the FETs (12, 14). The NVM device (10) is erased by applying an erasing voltage to the erasing capacitor (26) and applying ground voltage to the sources of the FETs (12, 14) and to the programming capacitor (28). Data is read from the NVM device (10) by sensing a voltage level at the drains of the FETs (12, 14) while applying a logic high voltage to the source of the p-channel FET (12), a logic low voltage to the source of the n-channel FET (14), and a reading voltage to the programming capacitor (28).

REFERENCES:
patent: 5027171 (1991-06-01), Reedy et al.
patent: 5465231 (1995-11-01), Ohsaki
patent: 5587945 (1996-12-01), Lin et al.
patent: 5604700 (1997-02-01), Parris et al.
patent: 5754471 (1998-05-01), Peng et al.

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