Single level bipolar ECL flip flop

Details Single level bipolar ECL flip flop Single level bipolar ECL flip flop

1991-10-10

1993-06-15

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 3072722, H03K 1920, H03K 3289

Patent

active

052202127

ABSTRACT:
An ECL OR gate circuit, or a logical equivalent AND gate circuit, is provided whereby the input signals are both referenced to the same bias reference signal such that the propagation delay between each input port to the output port of the gate is substantially equivalent. Also provided is an improved ECL flip flop circuit using the ECL OR (or AND) circuit taught in accordance with the teachings of this invention for a faster ECL flip flop. In accordance with the teachings of this invention, a flip flop clock input signal is referenced to the same bias reference signal as the flip flop data input signal such that the propagation delay between the clock input to the output stage is substantially the same as the data input to the output stage.

REFERENCES:
patent: 4675553 (1987-06-01), Price et al.
patent: 4841168 (1989-06-01), Kubota
patent: 4970417 (1990-11-01), Kubota

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