Electricity: electrical systems and devices – Miscellaneous
Patent
1981-09-08
1983-05-31
Kucia, R. R.
Electricity: electrical systems and devices
Miscellaneous
174 52PE, 174 685, 361398, 361414, 361421, H05K 118
Patent
active
043863892
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention pertains to the burn-in of integrated semiconductor circuits and more particularly to a burn-in tape for exercising such circuits.
BACKGROUND ART
Integrated semiconductor circuits have the potential for operating for long periods of time without failure. However, a substantial percentage of such circuits fail within the first few hours or days of operation due to marginal defects in manufacture. Such marginal circuits frequently test good under initial screening, but fail shortly thereafter. it is therefore incumbent upon the manufacturer of such circuits to burn-in each of the circuits for a period of time at elevated voltages and temperatures to cause failure of the marginal circuits before shipment. Without burn-in a substantial number of marginal circuits could be shipped to users and these circuits would be installed in the user's products only to fail a short time later. A failure of a component under such circumstances has severe economic impacts on both the user and the producer of integrated circuits.
Heretofore, integrated circuits have been burned-in after the circuits have been packaged in the manner that they will be delivered to the customer. A group of packaged circuits are mounted on a convential circuit board which has a plurality of sockets. The board is then placed in an oven for operating the circuits under stress. Within the oven the integrated circuits are cycled through their operational states while an elevated voltage is supplied thereto and the temperature is set to a stress level. After operating for a fixed number of hours in this environment, most of the marginal circuits fail and these circuits are discarded. The remainder of the circuits have been proven reliable and can therefore safely be shipped to the customers.
As noted above, the burn-in of each individual circuit is essential but this is a very expensive process. For each marginal circuit that is discarded there is a complete loss of the labor involved in inserting the circuit into the package as well as the cost of the package itself. In mass production operations, a great number of test boards and ovens are required to accommodate the volume of circuits which are being manufactured. The ovens and stress testing boards together with the labor involved in the handling of the circuits represent a substantial manufacturing expense.
In view of these problems there exists a need for apparatus for burn-in of integrated semiconductor memory circuits to reduce the labor required for such burn-in and to prevent the loss of packages for defective circuits.
DISCLOSURE OF THE INVENTION
The present invention comprises a tape for burning-in a plurality of integrated circuits. The tape comprises an elongate, nonconductive backing together with a plurality of noncrossing conductors bonded to the backing. The conductors can be fabricated from a single layer of metallization on the backing. The conductors extend along the backing for connection to a plurality of the integrated circuits for supplying signals thereto for concurrently exercising the integrated circuits.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following detailed description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a plan view of a burn-in tape having an integrated circuit semiconductor memory connected thereto; and
FIG. 2 is a schematic diagram of a burn in circuit for use in conjunction with the tape of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
A procedure termed "tape bonding" has been widely used in the semiconductor industry for connecting bonding pads on an integrated circuit to the pins in the circuit package. The burn-in tape of the present invention is illustrated in reference to FIG. 1. After a silicon wafer has undergone fabrication to produce a plurality of replicated circuits, the wafer is cut to separate each of the circuits to be an individual chip. An
REFERENCES:
patent: 3832769 (1974-09-01), Olyphant et al.
patent: 3838984 (1974-10-01), Crane et al.
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4056773 (1977-11-01), Sullivan
patent: 4064552 (1977-12-01), Angelucci et al.
patent: 4132856 (1979-01-01), Hutchinson
patent: 4209355 (1980-06-01), Burns
patent: 4281449 (1981-08-01), Ports et al.
Oswald et al., Automated Tape Carrier Bonding for Hybrids, Solid State Technology, Mar. 1978, pp. 39 to 48.
Kucia R. R.
Mostek Corporation
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