Single-layer autorouter

Details Single-layer autorouter Single-layer autorouter

2000-04-24

2001-11-20

Picardat, Kevin M. (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S107000, C438S108000, C438S612000, C438S613000

Reexamination Certificate

active

06319752

ABSTRACT:

FIELD OF THE INVENTION
The present application relates to manufacturing integrated circuit packages, and more specifically, to an autorouter for routing the die bumps to the package pins in an advanced integrated circuit package.
BACKGROUND ART
With the increasing complexity of large-scale integrated circuit chips, the number of input and output connections that have to be made to a chip has correspondingly increased. This trend has encouraged the evolution from dual in-line chip packages, which have two parallel rows of connection pins, to smaller and denser leadless chip carriers. Leadless chip carriers generally consist of a package containing a square plate of ceramic, such as alumina, which forms a chip carrier or base onto which a chip is mounted. The chip carrier is then surface mounted, usually onto a generally larger printed circuit board or other ceramic chip carriers, simply by placing the carrier on top of corresponding contact pads which mirror those contact pads of the chip carrier.
An electrical and mechanical connection is then made by soldering the chip carrier to this generally larger board by reflow soldering. Electrical connection paths within the leadless chip carrier allow the pads of the chip to be brought to external contact pads formed around each of the four sides of the ceramic base of the carrier. One technique for providing the electrical connection path comprises wire bonding of the leads of the chip to the external contacts. During this process very thin wires may be manually or automatically placed between the die pads and the bond fingers of the package to provide the electrical connections. This arrangement is less cumbersome than mounting dual in-line packages onto a board and allows greater density of input and output connections to be achieved.
In order to eliminate the expense, and complexity of wire bonding process, a so-called flip-chip technology was initiated. In this technology a bumped chip or die which carries a pad arrangement on a major top surface is turned upside-down, i.e. flipped, allowing direct coupling between the pads and matching contacts on the main circuit board or the chip carrier. The direct connection is facilitated by growing solder or gold bumps formed on the chip's input/output terminals. The flipped bumped chip is otherwise referred to as a flip-chip. The flip-chip is then aligned to the chip carrier and all connections are made simultaneously by reflowing the solder.
As schematically illustrated in
FIG. 1
, a flip-chip package
10
comprises a die
12
mounted on a die carrier or package
14
. The die
12
includes an array of bumps
16
which are bonded to the package
14
. Pins
18
corresponding to the bumps
16
are provided on the package
14
for connecting the flip-chip package
10
to a printed circuit board (PCB)
20
.
One of the first steps in the flip-chip package design is routing the bumps
16
to the package pins
18
. Traditional drafting packages commonly used for traditional IC package design have proven inadequate for advanced IC package design, such as flip-chip package design. Designer productivity and the quality of the final results are limited due to the lack of specialized capabilities in the tool, such as the ability to treat the chip and the chip carrier as a single open area as required for flip-chip package design.
Traditional PCB layout tools and software based on them are likewise limited in their usefulness for advanced IC package design. For example, because PCB layout tools focus on managing complex logical interconnects among large number of nets and components, they typically draw data from netlists. By contrast, the logic of a single-chip package is relatively simple—designers focus on connecting the chip bump to the most convenient package pin for maximum density.
While drafting packages and modified PCB layout tools can be used to design flip-chip packages in low volumes, the design process is slow and the results rarely optimized for production. Therefore, when manufacturing companies begin to adopt advanced IC packaging in higher volumes, routing tools developed specifically for the unique challenges of IC package design become necessary to achieve higher throughput and manufacturing yields.
Accordingly, it would be desirable to create a single-layer autorouter for routing interconnects in advanced IC packages such as flip-chip packages.
SUMMARY OF THE INVENTION
The present invention offers a novel method of automatically routing connections from bumps on a die to package pins in an advanced IC package such as a flip-chip package. The method involves creating graphic presentations of the die having bumps and the package having pins, and placing the graphic presentation of the die into the graphic presentation of the package. If a netlist identifying interconnections between the bumps and the pins is available, a route from a bump on the die to a corresponding package pin identified in the netlist is generated in accordance with preset requirements.
However, if the netlist is not available, the method involves generating a route from the bump to any package pin in accordance with the preset requirements.
In accordance with a preferred embodiment of the invention, the preset requirements may include:
providing the shortest route from the bump to the pin.
providing a route from the bump to the pin that does not cross any route from another bump to another pin.
maintaining a distance between routes from the bumps to the pins greater than a predetermined value.
The graphical presentation of the die may be created using a computer-aided design tool. The graphic presentation of the package may be created using Advanced Package Design software.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.


REFERENCES:
patent: 5399898 (1995-03-01), Rostoker
patent: 5957370 (1999-09-01), Galloway

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