Single latch data circuit in a multiple level cell...

Details Single latch data circuit in a multiple level cell... Single latch data circuit in a multiple level cell...

2006-08-18

2008-08-26

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185210

Reexamination Certificate

active

07417894

ABSTRACT:
A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.

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