Single interconnect, multi-bit interface

Details Single interconnect, multi-bit interface Single interconnect, multi-bit interface

2001-08-27

2002-11-05

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

To or from multi-level codes

C341S057000, C341S061000, C341S102000, C341S103000

Reexamination Certificate

active

06476736

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to space-saving signal transmission and more particularly to a multi-bit interface that utilizes a single interconnect to transmit a control or data signal.
BACKGROUND OF THE INVENTION
To provide signal paths between circuit blocks of an integrated circuit (IC), connection layers such as metal layers or polysilicon layers are used. These connection layers, also known as interconnects, require some finite width and thickness to ensure reliability of the interconnect and signal integrity thereof. When numerous signal paths are required between circuit blocks, the routing congestion caused by placement of the associated interconnects will increase the overall size of the IC and thus increase the cost of the product. That congestion has an increased effect when the area between the circuit blocks is limited. A further problem arises when numerous tightly-spaced functional blocks require a high number of signal paths between them. The associated numerous interconnects will cause even more IC area congestion that will further increase the IC size and associated cost.
Interconnect congestion often occurs when programmability is added to a function that is implemented in a relatively small area of the IC. For example, an Input/Output pad cell that requires programmability to adjust either the output slew rate or the output drive strength, or both, may use an analog circuit controlled by digital signals to accomplish the adjustment. Many digital control-signals may be required to achieve the desired programmable range of the controlled analog circuit. Those digital control signals typically require numerous signal paths between the circuit block generating those signals and the controlled analog circuit. The associated interconnects of those paths will add significantly to the IC area congestion when attempting the physical implementation, i.e., routing, of those interconnects.
One method to reduce the number of associated interconnects for the required digital control signals is to utilize a digital decoder proximate to the circuit of the functional block receiving those control bits. This can reduce the number of interconnects required between the circuit block generating those signals and the receiving circuit.
FIG. 1
shows a block diagram that performs such a function. Initiator
100
generates Y signals for up to 2
Y
control bits. The Y signals are provided to block under control
110
via leads
105
. Leads
105
must have Y leads.
However, the number of leads can be reduced only to N, where n is determined from the constraint:
2
N-1
<# of control bits≦2
N
.
Thus, if
9
control bits are required, N is
4
. For this case, the interconnect that provides the bit for the ninth control signal may be infrequently used. Consequently, that interconnect is inefficient since it wastes IC area, more so than the inefficiency caused by the other N-
1
interconnects.
Another method uses a single-wire interface, but requires a data serializer that shifts the parallel information to serial information. The time required to communicate the serial data over the single wire is dependent upon the number of bits and is greater than the time required to transfer the parallel information if the clock period of the parallel information transfer is less than the sum of the clock periods needed to transfer the serial data. A variation of this method may utilize a sum of the clock periods for the serial data transfer that is less than the clock period for the parallel information transfer. The problem with this variation is that a high speed clock must be derived from the system clock. Such derivation will require extra circuitry in addition to the extra circuitry required for the parallel-to-serial and the serial-to-parallel shift registers. Moreover, the serial information must be received in its entirety before any parallel information can be discerned. That would require multiple clock periods equal to the number of bits serially transmitted. Consequently, time is wasted for the second and additional clock periods required to receive the serially transmitted data, regardless of the clock speed.
Accordingly, a need exists that will provide the required number of control signals while further reducing the number of associated interconnects or that will require minimal additional circuitry and time to relay the control signals. The present invention meets this need.
SUMMARY OF THE INVENTION
The present invention overcomes the disadvantages and limitations of the prior art by providing a method to relieve the routing congestion described above by further reducing the number of interconnects to be routed, especially in a confined area. To that end, a digitally encoded signal is transmitted over a single interconnect that does not significantly add congestion or complexity on the IC, active silicon area when implemented on a silicon-based IC or additional time for signal transmission. The present invention achieves that transmission by providing a scaled current signal that varies depending on the desired digital control signal.
Numerous other advantages and features of the present invention will become readily apparent from the following detailed description of the invention and the embodiment thereof, from the claims and from the accompanying drawings in which details of the invention are fully and completely disclosed as a part of this specification.


REFERENCES:
patent: 4532638 (1985-07-01), Lagger et al.
patent: 5222105 (1993-06-01), Kinney et al.
patent: 5334978 (1994-08-01), Halliday
patent: 6104321 (2000-08-01), Akagiri

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