Single-instruction-multiple-data processing in a multimedia sign

Details Single-instruction-multiple-data processing in a multimedia sign Single-instruction-multiple-data processing in a multimedia sign

1996-08-19

2000-05-02

Pan, Daniel H.

Electrical computers and digital processing systems: processing

Processing architecture

Vector processor

712 4, 712 5, 712 13, 712228, 712 23, 708441, G06F 9305, G06F 1320, G06F 938

Patent

active

060584653

ABSTRACT:
A vector processor architecture provides vector registers of fixed size having data elements of programmable size and type. The type and size for data elements are defined by instructions which manipulate operands associated with the vector registers. The data size defined by an instruction determines the number of the data elements in a vector register and the number of parallel operations performed to complete the instruction. One embodiment of the invention supports 8-bit, 9-bit, 16-bit, and 32-bit data element sizes of integer type for all sizes and floating point data type for the 32-bit data elements.

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