Single instruction for multiple loops

Details Single instruction for multiple loops Single instruction for multiple loops

2005-01-11

2005-01-11

Dam, Tuan (Department: 2122)

Data processing: software development, installation, and managem

Software program development tool

Translation of code

C717S119000, C717S150000, C712S022000

Reexamination Certificate

active

06842895

ABSTRACT:
Embodiments of the present invention relate generally to the manner in which processors execute multiple loop instructions. That is, embodiments of the invention relate to the organization of multiple loop constructs, such as, for example, nested loops, to achieve improved performance during loop execution. One embodiment contemplates a single instruction that provides for execution of other instructions of a set of instructions in accordance with multiple looping constructs. Another embodiment contemplates a single-loop instruction suitable for terminating on multiple termination conditions.

REFERENCES:
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patent: 6085315 (2000-07-01), Fleck et al.
Hensley et al, “Active Page Architectures for Media Processing”, First Workshop on Media Processors and DSPs, 32nd Annual Symposium on Microarchitecture, http://citeseer.nj.nec.com/hensley99a, pp.: 1-10, Nov. 1999.*
Warter et al, “Enhanced Modulo Scheduling for Loops with Conditional branches”, MICRO-25 Conference Proceedings, pp.: 1-10, Dec. 1992.*
Albert et al., “Data Parallel Computers and the FORALL Statements”, IEEE, pp.: 390-396, 1990.*
Stoodley et al., “Software Pipelining Loops With Conditional Branches”, IEEE, pp.: 262-273, 1996.

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