Single gate oxide electrostatic discharge protection circuit

Details Single gate oxide electrostatic discharge protection circuit Single gate oxide electrostatic discharge protection circuit

1999-03-19

2002-10-01

Leja, Ronald W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C257S355000

Reexamination Certificate

active

06459553

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to over voltage protection circuits for protecting other circuits from higher than desired voltage levels, and more particularly to electrostatic discharge (ESD) protection circuits for protecting an input to a protected circuit.
BACKGROUND OF THE INVENTION
There is a constant challenge to continuously design smaller, faster and more complicated integrated circuits to provide increased functionality for multimedia applications and other applications. With the continued demand for higher speed and lower power consumption integrated circuits a need exists for simple, low cost and reliable over voltage protection circuits. Graphics controller chips, like many integrated circuit devices, utilize CMOS, logic cores, and associated I/O pads as part of their circuit makeup. I/O pads can include, for example, input/output buffers coupled to a common pad or pin. For example, CMOS based video graphics chips with 128 input/output ports (I/O ports) are required to operate at clock speeds of 125 MHz to 250 MHz or higher. Such devices may use a 2.5 V or 1.8 V power supplies for much of their logic to reduce power consumption. One way to increase the operating speed of such devices is to decrease the gate length of core circuitry transistors. However, a decrease in the gate length and gate oxide thickness of MOS devices can reduce safe operating voltage to lower levels.
For example, where an integrated circuit contains digital circuitry that operates from a 1.8 V source and is fabricated using silicon dioxide gate thickness of 30 Angstroms, a resulting safe operating voltage may be approximately 2.8 V. Such IC's must often connect with more conventional digital devices that operate at 5 V or 3.3 V. A problem arises when the core logic circuitry (operating at 1.8 V) receives 5 V digital input signals from peripheral devices on input pins (or I/O pins). Such standard 5 V input signals or 3.3 V input signals can cause damage if suitable voltage protection is not incorporated. Also, smaller devices can be more susceptible to electrostatic discharges that are received on power pads, input/output pads (I/O pads) or other pads.
As is known, input/output pads and power pads on integrated circuits require some form of ESD protection circuitry. A principal role of such circuits is to sink current from the ESD source to decrease a voltage level applied to the node or pad. As smaller gate oxide thicknesses are used to increase speed and density of integrated circuits, protecting against ESD damages becomes more difficult. In addition to withstanding ESD energy, single gate oxide transistors must also withstand varying supply voltage operating ranges. For example, external circuits may provide 5 V input signals during normal operating modes. Although a combination of thick gate and thin gate devices can make it easier to design ESD protection circuitry, it introduces another gate thickness and increases the number of processing steps required to fabricate the IC. This adds to the expense of the integrated circuit. In addition, dual gate oxide protection circuits such as those using 1.8 V or 3.3 V supply voltages typically cannot withstand a 5 V signal during normal operation.
As shown in
FIG. 1
, a conventional ESD protection circuit
10
is shown that may be used, for example, with a 3.3 V supply voltage. The circuit
10
protects a circuit to be protected
12
such as an input/output (I/O) prebuffer, buffer circuitry, core logic or any other suitable logic, which receives an input signal or generates an output signal on a node
14
. The node
14
may be connected to a pad
16
that may, if desired, be accessible to an external integrated circuit. The ESD protection circuit
10
includes a low pass filter
18
that includes a capacitor
20
and a resistor
22
. An nmos transistor
24
has its gate connected to the node between the capacitor and resistor. Such a circuit may be useful, for example, with thick gate oxide devices that, for example, accommodate a 3.3 V core logic voltage or node voltage. However, when a lower supply voltage is used for the core logic such as 2.5 V or 1.8 V, the circuit to be protected must also be compatible typically with a higher input signal (5 V) or 3.3 V input signal to interface with older external circuits. With a single gate oxide device used as part of an ESD protection circuit, and having, for example, a 0.25 micrometer length and 50 Å gate thickness, when a 5 V input voltage is applied to the pad, the transistor
24
will receive an excessive gate to source voltage during normal operation which over time can degrade the electrostatic discharge protection device. Accordingly, it would be desirable to have a circuit that is relatively inexpensive that utilizes a single gate oxide design to reduce costs while also allowing suitable protection against electrostatic discharge damage. Moreover, it would be advantageous if the electrostatic protection circuitry were effectively disabled during normal operations so that current is not drawn unnecessarily.
Consequently there exists a need for an ESD protection circuit that can be used for low supply voltage circuits while also withstanding higher input signal voltages. It would desirable if the protection circuit were a single gate oxide circuit.


REFERENCES:
patent: 5745323 (1998-04-01), English et al.
patent: 5946177 (1999-08-01), Miller et al.
patent: 5956219 (1999-09-01), Maloney
“Electrostatic Discharge (ESD) in Integrated Circuits”, Continuing Education in Engineering, University Extension, University of California.
Berkeley, San Francisco, CA (Sep.-Oct., 1996).

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