Single-flux-quantum multiply-accumulator

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G06F 752

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active

052894002

ABSTRACT:
A serial multiplier for multiplying two n-bit numbers is provided in which a shift register having a total of n destructive read out cells contains a separate bit of a first multiplicand in each cell. A string of (2n-1) non-destructive read out cells is provided to receive the second multiplicand. Each of the first n cells of the string of non-destructive readout cells contain a separate bit of the second multiplicand. Each bit of the first multiplicand is serially multiplied with the series of bits of said second multiplicand. After each such multiplication, each bit of the second multiplicand is moved to the next adjacent cell. The partial product of the multiplication is stored in a string of 2n T flip-flop cells. Each of the T flip-flop cells has a carry path to the next adjacent T flip-flop cell. Timing means are provided to regulate and initiate the multiplication.

REFERENCES:
patent: 3610907 (1969-01-01), Taylor
patent: 3617723 (1971-11-01), Melvin
patent: 4970676 (1990-11-01), Fling
patent: 5124941 (1992-06-01), Smith
patent: 5150321 (1992-09-01), Keating
K. K. Likharev and V. K. Semenov, "RSFQ Logic/Memory Family: A New Josephson-Junction Technology For Sub-Tetrahertz-Clock-Frequency Digital Systems", IEE Transactions on Applied Superconductivity, vol. 1, No. 1, Mar. 1991 (pp. 3-28).

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