Single event upset resistant semiconductor circuit element

Details Single event upset resistant semiconductor circuit element Single event upset resistant semiconductor circuit element

2001-05-16

2003-04-15

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Hardware for storage elements

Magnetic

C365S052000, C365S063000

Reexamination Certificate

active

06549443

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a single event upset resistant semiconductor circuit element, and more particularly to a single event upset resistant semiconductor circuit element formed of a plurality of parallel-connected semiconductor cell elements.
BACKGROUND OF THE INVENTION
A single event upset (SEU) is a type of electrical disturbance that can affect microelectronic devices. SEUs have multiple causes. In one instance, an SEU may be caused by a cosmic ray striking the microelectronic device. A cosmic ray is an exceedingly high energy particle from space. Cosmic rays consist mostly of protons but may also be heavier atomic nuclei. They may have energies of a billion electron volts (more energetic than many high energy particles created on earth in the most powerful particle accelerators), and are moving at nearly the speed of light. The earth's magnetic field deflects and its atmosphere absorbs most cosmic rays. Therefore, people and objects on the earth's surface are not highly affected. However, they do affect spacecraft and high-flying aircraft. Spacecraft and aircraft at high latitudes are more affected due to orientation of the earth's magnetic field.
In another instance, an SEU may be caused by an alpha particle striking the microelectronic device. Alpha particles are helium nuclei and are emitted from large atoms as a result of radioactive decay. Since the alpha particle does not contain any electrons, it has a positive charge. Alpha particles are typically present as low-level background radiation at the Earth's surface, and occur as a result of the decay of naturally occurring radioactive isotopes. A common source of alpha particles that may affect microelectronic devices is the minute amount of radioactive isotopes present in typical packaging materials.
Neutrons are another type of energetic particles that can affect electronic devices. Energetic neutrons are produced by nuclear reactions, collisions of protons with matter or by interactions between cosmic rays and the earth's atmosphere. Due to their lack of charge, they are able to deeply penetrate electronic devices, which can cause SEU effects in microelectronic devices.
Energetic particles th at strike microelectronic devices may adversely affect the operation of the electronic circuits. In particular, an energetic particle that hits a semiconductor memory cell element can cause the cell element to operate incorrectly, and can therefore cause the memory cell to change states (i.e., a single event upset or SEU). A memory cell corrupted by an energetic particle may cause severe problems, such as improper operation of a computer using an affected memory. For example, if a memory state change occurs in a critical memory component such as a processor program or data stack, the CPU may operate improperly after accessing the stack. It should be noted that although the effects of energetic particles on semiconductor memory cells are the most troublesome because the effect of an SEU disturbance may be “held” for some time, energetic particles in other circuitry also may be problematic. For instance, if a transistor in a combinational logic device is hit by radiation at a critical time, the logic device output may be affected and the output change may cause an error, which may be propagated through any subsequent circuitry.
An SEU typically is caused by electron-hole pairs created by, and along the path of, an energetic particle as it passes through a semiconductor device such as a memory cell. If the energetic particle generates a sufficient amount of charge in a critical volume of a semiconductor circuit element, then the logic state of the semiconductor circuit element may be corrupted. Either N-channel or P-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) may be upset by an energetic particle. The primary upset condition of concern is for an “off” device to be momentarily turned “on” by the generated charge.
FIG. 1
shows a representative metal-oxide-semiconductor (MOS) N-channel enhancement mode MOSFET and its schematic symbol. The N-channel MOSFET has a gate terminal G, a source terminal S, and a drain terminal D. The gate controls a channel region between the source and drain such that current flows in the device when the gate voltage is sufficiently positive with respect to the source terminal. When an energetic particle “R” strikes the semiconductor material, it may generate electron-hole pairs as shown by the respective positive and negative symbols. As can be seen from the figure, when the energetic particle “R” passes through the device, it may cause regions of accumulated negative and positive charge which may mimic the affect of gate voltage. Therefore, the energetic particle may momentarily affect operation of the transistor and may cause the transistor to effectively be biased “on”.
FIG. 2
shows a P-channel MOSFET and its schematic symbol. In contrast to the N-channel MOSFET, the P-channel MOSFET source and drain reside in an N-well, which provides electrical isolation and the appropriate semiconductor material polarity for fabrication of the complementary P-channel MOSFET co-resident with N-channel MOSFETs. As with the N-channel MOSFET, an energetic particle can affect the P-channel MOSFET and may bias the transistor “on”. It should be noted that an energetic particle strike in the N-well region may also cause undesirable effects that result in a transistor malfunction.
N-channel and P-channel MOSFETs are used together to implement Complementary Metal Oxide Semiconductor (CMOS) circuits that are well known in the art. An example basic CMOS circuit is illustrated in
FIG. 3
which shows a prior art inverter and its typical schematic symbol. The prior art inverter is composed of a P-channel MOSFET and an N-channel MOSFET connected as shown. If the input is at a high voltage level (i.e., a logic one), the P-channel MOSFET will be biased off while the N-channel MOSFET will be biased on. The P-channel MOSFET will act as essentially an open switch and the N-channel MOSFET will act as a closed switch in series with a small resistance connected to ground. Therefore the output will be a low voltage level (off, or a logic zero). Conversely, if the input is low, the P-channel MOSFET will be biased on and the N-channel will be biased off. The N-channel MOSFET will therefore act as an open switch and the P-channel MOSFET will act as a closed switch in series with a small resistance connected to V
DD
. The inverter output will therefore be a high voltage level (on, or a logic one). A significant benefit of the CMOS circuit topology is that in either static logic state, no current flows from V
DD
to ground, so the power consumption is extremely low.
FIG. 4
shows a graph of the output voltage of the prior art inverter during an SEU occurrence where the N-channel MOSFET is biased off and the output of the prior art inverter is at a high voltage level. Upon a strike by an energetic particle, the N-channel MOSFET may be momentarily biased on. The result is a condition where both MOSFETs are biased on, and a voltage division occurs, represented by
FIG. 3A
with both switches closed. The output voltage in the prior art inverter may swing towards about one-half of the supply voltage V
DD
, placing the output voltage at an indeterminate level for a period of time. Therefore, the output may change state, and may even oscillate between output states (the threshold voltage of one-half V
DD
is typically a decision level below which the output is a logic zero and above which the output is a logic one). This is an undesirable condition and may lead to other errors.
FIG. 5
shows a prior art memory cell formed of two inverters. A logic one on the input will be inverted twice, producing a logic one at the output. This regenerative positive feedback results in persistent storage of the input state in the circuit. Any disturbance to this memory cell that causes the stored state to be altered will appear on the output and will be persistently stored

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