Single event upset immune oscillator circuit

Details Single event upset immune oscillator circuit Single event upset immune oscillator circuit

2000-09-21

2002-09-10

Kinkead, Arnold (Department: 2817)

Oscillators

Ring oscillators

C331S034000, C331S00100A, C327S176000

Reexamination Certificate

active

06448862

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to electrical circuits in general, and in particular to oscillator circuits. Still more particularly, the present invention relates to a single event effect immune oscillator circuit.
2. Description of the Prior Art
Oscillator circuits are commonly found in clock generation circuits, phase-locked loop circuits, and timing circuits. In environments having a relatively high-level of radiation, such as satellite orbital space, electronic devices that utilize oscillator circuits are more susceptible to single event effects (SEEs). These SEEs are typically caused by electron-hole pairs created by, and travelling along the path of, a single energetic particle as it passes through the oscillator circuit. Should the energetic particle generate a critical charge within the diffusion node of the oscillator circuit, a false pulse will be generated at the output of the oscillator circuit.
Referring now to the drawings and in particular to
FIG. 1
, there is illustrated a schematic diagram of a typical oscillator circuit according to the prior art. As shown, an oscillator circuit
10
includes invertors
11
a
-
11
d
and a two-input NAND gate
12
, all connected in series. In this implementation, the output of invertor lid also serves as the output for oscillator circuit
10
. In addition, the pulse within oscillator circuit
10
can be turned off by de-asserting an enable input
13
. For oscillator circuit
10
, the diffusion nodes in each of invertors
11
a
-
11
d
are very susceptible to SEEs. In order to reduce the susceptibility of oscillator circuit
10
to SEEs, very large n-channel and p-channel transistors are typically utilized to form invertors
11
a
-
11
d
. While the effects of SEEs can be somewhat reduced with this approach, false pulses may still be generated by SEEs. Thus, the above-mentioned solution would not be acceptable for oscillator applications that are very sensitive to SEEs.
With reference now to
FIG. 2
, there is illustrated a schematic diagram of a SEE immune oscillator circuit, according to the prior art. Oscillator circuit
20
eliminates SEE transients by utilizing a redundancy scheme. As shown, oscillator circuit
20
includes three identical sets of oscillator circuits
20
a
-
20
c
, each of which is similar to oscillator circuit
10
from FIG.
1
. Output
23
from each of oscillator circuits
20
a
-
20
c
are coupled to a voter
21
. Voter
21
is designed to filter out any SEE transient pulses by allowing a pulse to occur at output
24
only if at least two of the input pulses at output
23
are identical. While oscillator circuit
20
having a voting scheme may eliminate SEE transient pulses at output
24
, the circuit complexity is tripled due to the three-fold increase in the number of devices from oscillator circuit
10
of FIG.
1
and the added requirements of synchronization as well as phase issues among oscillator circuits
20
a
-
20
c.
In addition, voter
21
itself may also be susceptible to SEEs.
Consequently, it is desirable to provide an improved oscillator circuit having a higher radiation tolerance. Radiation tolerance refers to the ability of an electronic device to withstand radiation without alteration of its electrical characteristics. An electronic device is said to be radiation tolerant if it can continue to function within specifications while experiencing SEEs.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a single event effect immune oscillator circuit includes an odd number of logic circuit blocks connecting in series to provide a continuous pulse signal at an output of the oscillator circuit. Each logic circuit block has a first input, a second input, and an output. For a series of logic circuit blocks i, where i=1 to n (n is an odd number), the output of a logic circuit block i is connected to a first input of a logic circuit block i+1. The output of the logic circuit block i is also connected to a first input of a logic circuit block i+x, wherein x is an odd number greater than one and less than or equal to n.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.


REFERENCES:
patent: 5182529 (1993-01-01), Chern
patent: 6005448 (1999-12-01), Pickering et al.

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