Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1999-05-12
2001-06-26
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S070000, C327S074000, C327S077000
Reexamination Certificate
active
06252433
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates generally to analog signal comparators, and more particularly, to an apparatus and method for combining existing analog comparators to produce a single event upset immune comparator for use in the outer space environment.
2. History of Related Art
Analog voltage comparators are used in almost every area of electronic circuitry, such as power supplies, data transmission and reception, and data acquisition. Typically, the comparator provides a logic-level signal at its output, depending on the relative voltage values present at each one of two inputs. The output voltage level is thus determined by which one of the inputs has a higher voltage level. For example, if the comparator has an input labeled “plus,” and an input labeled “minus,” then the output will go to a low logic-level if the minus input voltage value is higher than the voltage value present at the plus input. However, if the plus input voltage value is higher than that present at the minus input, the output will be driven to a high logic-level.
A Single Event Upset (SEU) typically refers to the interrupted function of a digital electronic circuit, usually occurring at the single-bit level, when a particle of ionizing radiation impacts upon the circuit and changes the logic-value of its output. The exact effect of any SEU depends on the particular device involved, and its relation to other components in a particular circuit. The generalized effect for a logic-dependent circuit is the changing of an output value from its normally expected level to the opposite (e.g., “1” to “0” or “0” to “1”). Such changes, induced by ionizing radiation, generally result in unexpected and undesirable circuit performance.
Due to the shielding effects of the earth environment, SEUs due to ionizing radiation are not normally considered as part of electronic circuit design. However, in the outer space environment, where electronic components may perform functions of a more critical nature (e.g., failure may result in the loss of life or a very expensive spacecraft), the SEU becomes part of many electronic design decisions.
SEU immune circuitry has been developed for various digital logic families. However, such circuitry (e.g. silicon-on-sapphire) may be prohibitively expensive or very difficult to procure in a timely fashion due to limited production runs. Other logic families, such as Complementary Metal Oxide Semiconductor (CMOS) logic, are SEU immune, but may not have the desired current-drive ability. Further, many digital logic SEU immune approaches have been advanced, but analog components which are SEU immune have not received the same attention by manufacturers.
Therefore, what is needed is a design approach to provide SEU immune comparators for use in the outer space environment which is relatively independent of the logic family employed, and does not require a prohibitively expensive technology for manufacture. Further, since conventional comparators are beset by the problem of offset voltage and currents at the inputs, it would be desirable to provide a SEU immune comparator design which accommodates such offset voltage and currents to produce a reliable comparator output even when the input voltages are fairly close to each other in value.
Further, since individual comparators are typically manufactured as dual, quad, or larger groupings of identical units in a single package, it would be desirable to provide a SEU immune comparator which takes advantage of multiple unit packaging and minimizes the use of non-identical components for enhanced reliability. In addition, since the power used and volume occupied by electronic circuitry is to be minimized in the outer space environment, it is desirable to provide a SEU comparator deign which makes use of the least possible number of electronic components so as to provide an attractive alternative to other methods which result in greater power consumption or larger amounts of circuit real estate consumed.
SUMMARY OF THE INVENTION
For the purposes of the present invention, the term “SEU immune” refers to a circuit which renders the probability of malfunction due to SEUs relatively low compared to conventional devices. In other words, while a SEU immune circuit will normally continue to function as expected by the designer during a single SEU event, it is within the realm of probability (although highly unlikely) for the SEU immune circuit to malfunction due to multiple, simultaneous SEU events.
The apparatus of the present invention can be embodied in several different configurations, dependent on the particular type of logic family used to implement the SEU-immune function, and whether the circuitry is designed to compensate for offset voltages and currents at comparator inputs.
For example, one implementation of a SEU immune comparator may comprise a pair of commonly-available open-collector output analog comparators, each having a plus input and a minus input. The first and second plus inputs are adapted to receive the output from an external circuit designed to provide a reference voltage for the plus inputs, and the minus inputs are adapted to receive the output from an external circuit designed to provide a reference voltage for the minus inputs. The open-collector outputs of the two comparators are connected together so as to provide a normally-low logic output. If it is desired to provide a normally-high logic output, then a SEU immune inverter is connected to the normally-low output and the reference voltage connections are reversed (i.e., the plus input reference voltage is now applied to the minus comparator inputs, and the minus input reference voltage is now applied to the plus comparator inputs).
If a non-open-collector logic family is used to design the SEU immune comparator, then a slightly different approach must be used. In this case, for a normally-low output, the comparator outputs are supplied to the input of a SEU immune AND gate. For a normally-high output, the comparator outputs are also not connected directly together, but are supplied to individual inputs of an SEU immune OR gate. However, in this case, the external circuitry reference voltages are not exchanged (i.e., the external circuitry reference voltage for the plus input remains connected to the comparator plus inputs, and the external circuitry reference voltage for the minus input remains connected to the minus comparator inputs).
When the circuit design requires compensation for voltage and/or current offsets which are present at the comparator inputs, a slightly different topology must be used. The difference in approach for this case lies in the use of duplicated external reference voltage circuitry which allows adjustment of the voltage level at the input of each comparator. That is, instead of using a single reference circuit to supply the plus inputs of each separate comparator, one plus external circuit typically drives one plus input of a single comparator. A second, duplicate, plus reference external circuit is used to drive the second plus input of the second comparator. Further, the external circuitry for the minus input is also duplicated. That is, the minus input for the first comparator is typically driven by a first minus reference external circuit, and the minus input for the second comparator is typically driven by a duplicate, minus reference external circuit. Each of the duplicate plus and minus reference circuits has the capability for voltage adjustment so as to enable matching the comparison trip points for the converter pair. With the exception of the duplicated circuitry, all of the circuit topologies described above remain the same, given the requirements for normally-low or normally-high output, and the use of open-collector, or non-open-collector logic families.
REFERENCES:
patent: 3599096 (1971-08-01), Stemples et al.
patent: 3624538 (1971-11-01), Gere et al.
patent: 3925633 (1975-12-01), Partridge
patent: 4101789 (1978-07-01), Ruhnau
patent: 4105900 (1978-08-01), Martin
patent: 4149160 (1979-04-01
Baker & Botts L.L.P.
Callahan Timothy P.
Luu An T.
Southwest Research Institute
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