Single-etch stop process for the manufacture of silicon-on-insul

Details Single-etch stop process for the manufacture of silicon-on-insul Single-etch stop process for the manufacture of silicon-on-insul

1996-01-11

1999-08-10

Dang, Trung

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Thinning of semiconductor substrate

438455, 438406, 438977, 148DIG12, H01L 21479

Patent

active

059373121

ABSTRACT:
A single-etch stop process for the manufacture of silicon-on-insulator wafers. The process includes forming a silicon-on-insulator bonded wafers comprising a substrate layer, an oxide layer, a device layer, and a device wafer. The device layer is situated between the device wafer and the oxide layer and the oxide layer is between the device layer and the substrate layer. The device wafer has a p.sup.+ or n.sup.+ conductivity type and a resistivity ranging from about 0.005 ohm-cm to about 0.1 ohm-cm. A portion of the device wafer is removed from the silicon-on-insulator bonded wafers and the remaining portion of the device wafer has a defect-free surface after such removal. The remaining portion of the device wafer is then etched to expose the device layer.

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