Single-error detecting and correcting system

Excavating

Patent

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371 377, 371 404, G06F 1110

Patent

active

050635654

ABSTRACT:
A single-error detecting and correcting system includes a first memory for storing data and outputting the stored data in response to an input address applied, the data having control data and error check data, and an error detector for checking in accordance with the check data whether the control data in data read from the first memory is in error and generating an error detect signal in accordance with the result of the error checking. An error corrector has a second memory for storing correction data and responds to the errror detect signal to correct the data read from the first memory in accordance with the correction data, to set the first memory to a write mode and to write the corrected data into the first memory.

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Creamer, et al., "Controlled Retry On Storage Errors", IBM TAB, vol. 11, No. 9, 2/1969 pp. 1100-1101.
Hsiao, "A Class of Optimal Minimum Odd Weight Column SEC DED Codes", IBM J. Res. Develop., pp. 395-401, Jul. 1970.

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