Single ended termination of clock for dual link DVI receiver

Details Single ended termination of clock for dual link DVI receiver Single ended termination of clock for dual link DVI receiver

2006-08-29

2006-08-29

Bayard, Emmanuel (Department: 2611)

Pulse or digital communications

Receivers

Interference or noise reduction

C375S356000, C375S372000, C375S257000

Reexamination Certificate

active

07099416

ABSTRACT:
A receiver includes clock termination circuitry that is capable of applying either a terminating impedance or a high impedance to a transmission path that carries a clock signal. When multiple of these receivers are used to service data links that share a clock signal, one of the clock termination circuits applies the terminating impedance to the transmission path that carries the clock signal while the other clock termination circuit(s) applies a high impedance to the transmission path. The receiver also includes a plurality of high rate serial bit stream buffers and a clock signal buffer along with the clock termination circuitry. In other embodiments, the receiver includes a deserializer and may include a controller. The receiver may service a dual link Digital Visual Interface.

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Digital Display Working Group, Digital Visual Interface DVI Revision 1.0, Apr. 2, 1999.

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