Single ended receiver circuit with hysteresis

Details Single ended receiver circuit with hysteresis Single ended receiver circuit with hysteresis

1987-06-29

1988-10-04

Zazworsky, John

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307491, 307497, 307501, 307304, H03K 5153, G01R 19165

Patent

active

047758074

ABSTRACT:
An improved on chip single ended integrated circuit receiver includes a first circuit arrangement for setting a first referenced voltage level for an incoming signal, a second circuit arrangement for generating a second referenced voltage level with hysteresis and a third circuit arrangement for correlating the incoming signal with the second referenced voltage level and outputting a signal representative of the incoming signal. The second circuit arrangement includes a four terminal MOS FET device whose substrate electrode is connected to an active node formed between a pair of MOS FET devices and controlled by the output signal from the third circuit arrangement.

REFERENCES:
patent: 3666970 (1972-05-01), Abbott et al.
patent: 3939365 (1976-02-01), Lindgren
patent: 4092548 (1978-05-01), Beilstein, Jr. et al.

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