Single-ended pulse gating circuit

Pulse or digital communications – Synchronizers – Self-synchronizing signal

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Details

375373, 327156, 327299, H04L 702

Patent

active

054636558

ABSTRACT:
The present invention provides a gating circuit having two separate paths for detecting even and odd bits. Each path includes an equal number of coupled flip-flops. After bit detection, combinational logic merges the two paths to provide an output signal. An optional reset signal initializes all flip-flops to a logic zero at the start of a data read operation.

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patent: 5124597 (1992-06-01), Stuebing et al.
patent: 5172397 (1992-12-01), Llewellyn
patent: 5220212 (1993-06-01), Sinh
patent: 5321702 (1994-06-01), Brown et al.

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