Single ended preamplifier having multiple first stage banks...

Details Single ended preamplifier having multiple first stage banks... Single ended preamplifier having multiple first stage banks...

2000-06-07

2003-03-25

Faber, Alan T. (Department: 2651)

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Head amplifier circuit

C360S067000, C360S063000

Reexamination Certificate

active

06538832

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to the field of information storage, more specifically to hard disk drives and in particular to preamplifier circuits.
BACKGROUND OF THE INVENTION
U.S. Pat. No. 5,831,888 entitled “Automatic Gain Control Circuit” and assigned to Texas Instruments Incorporated, the assignee of the present invention, sets forth generally the description of disk storage. Hard disk drives (HDD) are one type of disk storage that are particularly used in personal computers today. The HDD device generally includes a magnetic storage media, such as rotating disks or platters, a spindle motor, read/write heads, an actuator, a preamplifier, a read channel, a write channel, a servo controller, a memory and control circuitry to control the operation of the HDD and to properly interface the HDD to a host or system bus. The following U.S. Patents describe various aspects of HDD devices:
5,535,067
Frequency Controlled Reference
Issued
07/09/96
Generator
5,570,241
Single Channel, Multiple Head
10/29/96
Servo ...
5,862,005
Synchronous Detection Of Wide
01/19/99
BI-Phase ...
5,793,559
In Drive Correction Of Servo
08/11/98
Pattern ...
5,719,719
Magnetic Disk Drive With
02/17/98
Sensing ...
5,444,583
Disk Drive Having On-Board
08/22/95
Triggered ...
5,448,433
Disk Drive Information Storage
09/05/95
Device ...
5,208,556
Phase Lock Loop For Sector
05/04/93
Servo System
5,642,244
Method and Apparatus For
06/24/97
Switching ...
Prior art
FIG. 1
illustrates a disk/head assembly
12
and a preamplifier
14
. The preamplifier
14
handles both read functions and write functions. Not illustrated in
FIG. 1
, for clarity, is the Magentoresistive (MR) head. The unshown MR head works through magnetic media and it has both functions, read and write, with a different portion of the head performing each function. The write function portion of the MR head is inductive and the read function portion of the head acts as a magnetic resistive element. A write occurs through an inductive element to the magnetic media disk assembly
12
and a read occurs by sensing the magnetic shifts in the disk assembly
12
by using the resistive read element. The preamplifier
14
connects to the unshown MR head.
Prior art
FIG. 2
illustrates a portion of the read channel of preamplifier
14
of FIG.
1
. The resistive portion of the unshown MR head is represented by the resistors Rmr
1
-Rmr
6
. An initial amplification stage
18
of preamplifier
14
connects to the resistive portion Rmr of the MR head. Later gain stages
20
of preamplifier
14
are connected to the outputs of initial amplification stage
18
at nodes NA and MB. The read path outputs flow from the later gain stages
20
. The read channel inputs flow into preamplifier
14
from a head select logic stage. In typical mass storage devices of the HDD type, the preamplifier
14
may have as many as 1 to 8 channels. Transistor SW
1
represents the read channel input enabling MOS transistor for head
1
of the 6 heads illustrated in FIG.
2
. The other enabling MOS transistors for heads
2
-
6
are unillustrated for clarity. In the operational example explained below, since read head
1
is illustrated as the selected head, the input NPN transistors Q
2
-Q
6
for the other heads are illustrated in the off condition with their bases being connected to the integrated circuit ground.
The architecture of initial amplification stage
18
of preamplifier
14
is constructed as that of a single ended amplifier as opposed to a differential amplifier; the single ended amplifier uses only one transistor Q
11
to set the voltage on the load side of later gain stage
20
. (As is known to one of ordinary skill in the art of amplifier design, a differential amplifier uses two transistors to establish the voltages on nodes N and M, one transistor for node N and one transistor on node M.) On one side of the single ended amplifier, the bias current Ib travels through the load resistor R
1
and through the collector of transistor Q
11
to set the voltage on node M. On the other side of the single ended amplifier, the bias current Ib/∝ travels through the scaling resistor ∝R
1
to set the voltage on node N. (The reference character ∝ represents the scale factor for the resistor. In this example, the scale factor is 20 and so the scaling resistor is illustrated as
20
R
1
.) In hard disk drives, because of linearity problems during a read operation, the voltage on the read head (represented by VRmr) is biased up to a certain level, which is typically around 0.2 to 0.5 volts. This bias voltage VRmr is established through a feedback loop created by transconductance amplifier
22
across nodes M and N whose output is connected to the base of transistor Q
11
through MOS switch SW
1
. This, in essence, creates a pseudo-balanced output on the reader load resistors such as would exist if a differential amplifier were used in the initial amplification stage.
In operation of prior art
FIG. 2
, when head
1
is selected, NPN bipolar transistors Q
11
and Q
1
are on. Together with the load resistor R
1
, they form a cascode amplifier. A cascode amplifier is a high bandwidth amplifier. The transistor Q
1
is a common base amplifier and the transistor Q
11
acts as a common base amplifier. As the magnetic resistive head moves over data, the head resistance Rmr varies. This can be modeled by an alternating current ac signal in series with the Rrnr resistor. The transistors Q
1
and Q
11
amplify this signal. The ac signal goes to the load resistor R
1
and then to the base of emitter follower transistor Q
8
. Then, the signal goes to the node MB input of latter gain stage
20
that is a differential amplifier. The other input of the amplifier
20
is node NA that should be at a dc bias voltage equal to the voltage on the load resistor R
1
node MB. The node NA constant voltage side of the later gain stage amplifier
20
should not have an alternating current signal on it. The reference side of single ended initial amplification stage
18
consists of transistors Qb, Q
21
and the scaling resistor
20
R
1
. This supplies a current Ib/∝ through the scaling resistor
20
R
1
, which provides a voltage at node N. The transconductance amplifier
22
forms a feedback loop with the cascode amplifier Q
1
and Q
11
. The purpose of the loop is to make sure that node M dc voltage on the signal side of the load resistor R
1
is the same as the dc voltage on node N. If the dc voltage on node M and node N are the same, the input voltage on differential amplifier
20
at nodes NA. and nodes MB are the same. On node NA, there is no ac signal; on node MB there is an ac signal. If the dc voltages are equal, then the differential later gain stage amplifier
20
will amplify the ac signal and send it to further gain stages.
In operational summary of the example shown in prior art
FIG. 2
wherein head
1
of the 6 illustrated heads is selected, when the magnetic resistive head moves to select data at head
1
, an ac data signal appears on the resistive portion of the head represented by Rmr
1
. Transistors Q
1
and Q
11
amplify this data signal, by the load resistor R
1
and the data signal appears at node M. There is no ac signal at node N. The ac data signal at load resistor R
1
gets amplified by differential amplifier
20
and is output to further later gain stages. For selecting the read heads, the MOS switch SW
1
connects the base of transistor Q
1
to capacitor C
1
. When this occurs, all the current that goes through the load resistor R
1
and transistor Q
11
goes through transistor Q
1
. As stated earlier, all the other input transistors Q
2
-Q
6
are not selected as connecting their bases to integrated circuit ground turns them off.
Supply noise is a problem for single ended preamplifier stages as it adversely affects the bit error rate of the preamplifier. That is, if noise is present, the preamplifier may incorrectly send the wrong data through the read channel. Noise may exist in several sources such as the Vcc power supply, ground and subst

Affiliated with

Also associated with

Rating

Single ended preamplifier having multiple first stage banks... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Single ended preamplifier having multiple first stage banks..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single ended preamplifier having multiple first stage banks... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3023940