Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-06-26
2003-12-30
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000, C345S204000, C345S205000, C345S211000, C345S212000, C345S214000, C326S063000, C326S080000, C326S081000, C327S333000
Reexamination Certificate
active
06670939
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a single-ended high-voltage level shifter for a TFT-LCD gate driver, and more particularly, to a single-ended high-voltage level shifter that minimizes the chip area of a TFT-LCD gate driver.
BACKGROUND OF THE INVENTION
A functional block diagram of a typical TFT-LCD gate driver with 256 output channels for XGA/SXGA display systems is shown in FIG.
1
. The gate driver includes a bidirection shift control register, an enable control, a level shifter and an output buffer. The bidirection shift control register, triggered synchronously by the rising edge of a shift clock (SCLK), is used to continuously shift the start pulses of the right data input/output (DIOR) or the left data input/output (DIOL) according to the right/left shift control signal (RL). Each output channel of the gate driver is gated asynchronously by the global-on control signal (XON) and the output-enabled signal (OE). Then the voltage level of each output channel of the gate driver is translated to drive the output buffer of the next stage.
A conventional implementation of the level shifter
21
and the output buffer
22
is shown in FIG.
2
. The level shifter
21
includes two high-voltage PMOS transistors M
1
, M
3
and two high-voltage NMOS transistors M
2
, M
4
. Herein, the high-voltage MOS transistor is different from the low-voltage MOS transistor in that the high-voltage MOS transistor withstands higher drain-to-source or gate-to-source voltage than that of the low-voltage MOS transistor, for example: 40V. The threshold voltage V
T
of the high-voltage MOS transistor is also higher than the low-voltage MOS transistor. For example, the threshold voltage of the high-voltage PMOS transistor is 1.7V, and the threshold voltage of the high-voltage NMOS transistor is 2.7V. The input signal IN is used to drive the transistor M
2
, and the complementary input signal INB is used to drive the transistor M
4
.
When the gate of the transistor M
2
receives an input low signal V
SS
, the low-voltage power supply, for example: −5V. The transistor M
2
is OFF and the transistor M
4
is ON. The voltage of node B is pulled to V
SS
, and the transistor M
1
is ON. The voltage of node A is then pulled to the high-voltage power supply V
DD
, for example: 25V~35V, then M
3
is OFF. As a result, the transistor M
6
is ON and the voltage of the output signal OUT is V
SS
. When the input signal IN applied at the gate of the transistor M
2
is changed from low to high, for example: −5V+3.3V=−1.7V, the transistor M
2
is ON, and the transistor M
4
is OFF. The voltage of node A is pulled to V
SS
and the transistor M
3
is ON. The voltage of node B is pulled to V
DD
. Then the transistor M
1
is OFF. Because the voltage of node A is V
SS
, the transistor M
5
is ON and the voltage of the output signal OUT is pulled to V
DD
.
The advantage of this conventional circuitry is that there is no static power consumption in the level shifter
21
. However, the sizes of the high-voltage transistors M
2
and M
4
have to be designed much larger than those of the high-voltage transistors M
1
and M
3
as the high level of the input signal does not differ much from the threshold voltage of the high-voltage transistors M
2
and M
4
. The reason is that when the high-voltage transistor M
2
(or M
4
) is ON, the voltage of node A (or B) should be pulled from the high-voltage power supply V
DD
to the low-voltage power supply V
SS
in a short period of time. Thus the sizes of the high-voltage transistors M
2
and M
4
have to be designed large enough to sustain the large current. In addition, the high level of the input signal is necessarily higher than the threshold voltage of the high-voltage transistors M
2
and M
4
(typical of 2.7V) in order to drive the level shifter shown in FIG.
2
.
FIG. 3
shows a circuit diagram having the level shifter
31
and the output buffer
32
connected together according to another prior art wherein the circuitry of the output buffer
32
is identical to that of the output buffer
22
shown in FIG.
2
. The low-voltage transistors M
7
and M
8
receive the input signal IN and the complementary input signal INB respectively. The source of the high-voltage transistor M
2
is connected to the drain of the low-voltage transistor M
7
and the source of the high-voltage transistor M
4
is connected to the drain of the low-voltage transistors M
8
. Both the gates of M
2
and M
4
are connected to a reference voltage V
RL
to limit the voltage of the drains of M
7
and M
8
not to exceed V
RL
-V
T
, for example: 5V−2.7V=2.3V. This is to prevent M
7
(or M
8
) from breakdown when the voltage of drain-to-source of M
7
(or M
8
) is excessively high. The advantage of this conventional circuitry is that the sizes of the high-voltage transistors M
2
and M
4
are not necessarily designed much larger than those of the high-voltage transistors M
1
and M
3
like the circuitry shown in FIG.
2
. This is due to the employment of the low-voltage transistors M
7
and M
8
. As a result, the chip area of the level shifter
31
is smaller than that of the level shifter
21
.
Although the level shifter
31
occupies smaller chip area than the level shifter
21
, the level shifter
31
still uses 4 high-voltage transistors that occupy significant chip area. Therefore, this plays an important role in determining the cost of the gate driver IC.
SUMMARY OF THE INVENTION
In view of the foregoing problems, the object of the invention is to provide a single-ended high-voltage level shifter for the TFT-LCD gate driver. Employing only two high-voltage transistors minimizes the chip area of the single-ended high-voltage level shifter. Implementing partial logic control circuitry in the level shifter further minifies the chip area of the TFT-LCD gate driver. Therefore, the total cost of the gate driver IC is significantly reduced.
The single-ended high-voltage level shifter for the TFT-LCD gate driver comprises (a) a high-voltage power supply and a low-voltage power supply; (b) a first low-voltage NMOS transistor, having its gate connected to an input signal and its source connected to the low-voltage power supply; (c) a high-voltage NMOS transistor, having its gate received a first reference voltage whose level is between the input-signal level and the high-voltage power supply, and having its source connected to the drain of the first low-voltage NMOS transistor; (d) a first high-voltage PMOS transistor, having its gate received a second reference voltage that keeps the first high-voltage PMOS transistor in ON-state and is at a level higher than the first reference voltage, and having its source connected to the high-voltage power supply, and having its drain connected to the drain of the high-voltage NMOS transistor and employed as the output end connected to an output driver of the next stage.
REFERENCES:
patent: 5973508 (1999-10-01), Nowak et al.
patent: 6359491 (2002-03-01), Cairns et al.
patent: 6522323 (2003-02-01), Sasaki et al.
patent: 6593920 (2003-07-01), Okumura et al.
Chao Chin-Chieh
Wang Chien-Kuo
Yang Tsen-Shau
Martine & Penilla LLP
Myson-Century, Inc.
Nguyen Jennifer T.
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