Single-ended balance-coded interface with embedded-timing

Details Single-ended balance-coded interface with embedded-timing Single-ended balance-coded interface with embedded-timing

2006-05-30

2006-05-30

Nguyen, John B (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

To or from minimum d.c. level codes

C341S060000, C341S059000

Reexamination Certificate

active

07053802

ABSTRACT:
An interface includes an encoder to receive a stream of input symbols and, in response, to output a corresponding stream of output symbols of substantially equal weight via multiple signal lines, which can improve noise/speed performance. The encoder outputs the stream of output symbols so that no output symbol is consecutively repeated. A repeat symbol is used to indicate that the current symbol is identical to the immediately preceding symbol. This encoding allows an interface receiving the stream of output symbols can extract a clock signal from the stream.

REFERENCES:
patent: 5625644 (1997-04-01), Myers
patent: 5970098 (1999-10-01), Herzberg
patent: 5996104 (1999-11-01), Herzberg
patent: 6151334 (2000-11-01), Kim et al.
patent: 6295010 (2001-09-01), Thiesfeld
patent: 6320520 (2001-11-01), Luby
patent: 6477502 (2002-11-01), Ananthpadmanabhan et al.
patent: 6734811 (2004-05-01), Cornelius

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