Single-ended balance-coded interface with embedded-timing

Details Single-ended balance-coded interface with embedded-timing Single-ended balance-coded interface with embedded-timing

2003-05-21

2004-05-11

Young, Brian (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

To or from minimum d.c. level codes

C341S060000, C341S059000, C341S102000

Reexamination Certificate

active

06734811

ABSTRACT:

FIELD OF THE INVENTION
Embodiments of invention relate generally to bus interfaces and, more specifically but not exclusively relate to encoded bus interfaces.
BACKGROUND INFORMATION
Modern bus systems for use in high-performance systems (e.g., a processor system) can operate at 400 MHz or more. Such high-speed systems can be susceptible to noise (e.g., supply noise due to switching of the circuits used to drive signals on the bus lines).
One solution is to use differential signaling schemes that help reduce sensitivity to common mode noise on the signal lines. However, differential signaling schemes have the disadvantage of doubling the number of signal lines and transceivers compared to single-ended schemes. Thus, for some applications, differential signaling may be undesirable. For example, some modern buses are 64-bits wide for data, thereby requiring 128 data signal lines. This relatively large number of data signal lines (and the associated transceivers) occupies valuable area on the chip(s) and wiring substrate (e.g., motherboard), which tends to increase the cost and complexity of the system.
On the other hand, if single-ended signal lines are used, in addition to the aforementioned noise sensitivity, the bus interfaces driving the signals on the signal lines can be “unbalanced”. That is, the number of logic low signals and logic high signals during a clock cycle may be different, resulting in a local net current flow in or out of a bus interface. This current flow can undesirably cause localized power supply noise (including simultaneously switching output (SSO) noise).
SUMMARY OF THE INVENTION
In accordance with aspects of embodiments of the present invention, an interface includes an encoder to receive a stream of input symbols and, in response, to output a corresponding stream of output symbols of substantially equal weight via multiple signal lines. In this context, a symbol refers to value of a preselected set of bits propagated on a selected set of signal lines. This balance-coded interface allows for relatively fast bus frequency with relatively low simultaneous switching output (SSO) noise.
In accordance with another aspect of embodiments of the present invention, an interface receiving the stream of output symbols can extract a clock signal from the stream. In this aspect, the encoder outputs the stream of output symbols so that no output symbol is consecutively repeated. In one embodiment, a repeat symbol is used to indicate that the current symbol is identical to the immediately preceding symbol. Thus, because no two consecutive output symbols are repeated, the receiving interface will be able to detect a signal transition on at least one of the signal lines. The receiving interface can use the detected transitions to generate a clock signal.
In still another aspect of the present invention, the encoder can output a MASK symbol to indicate that data is masked. This aspect can be advantageously used in memory applications, which typically define a mask bit in the interface.
In yet another aspect of the present invention, the interface can use symbols that are not used for data or mask symbols for command/control purposes. For example, in one embodiment, these “spare” symbols can be used to configure interconnect devices such as multiplexers and interleavers.


REFERENCES:
patent: 5625644 (1997-04-01), Myers
patent: 6151334 (2000-11-01), Kim et al.
patent: 6295010 (2001-09-01), Thiesfeld
patent: 6477502 (2002-11-01), Ananthpadmanabhan et al.

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