Single-end-zero receiver circuit

Details Single-end-zero receiver circuit Single-end-zero receiver circuit

1999-12-06

2003-05-27

Phu, Phuong (Department: 2631)

Pulse or digital communications

Receivers

C375S371000, C375S317000, C375S257000, C327S070000

Reexamination Certificate

active

06570934

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a single-end-zero receiver circuit for differential data.
A conventional single-end-zero receiver circuit for differential data will be described with reference to
FIGS. 1 and 2
.
FIG. 1
shows an example of conventional single-end-zero receiver circuits.
FIG. 1
shows a DATA+ input terminal
101
, a DATA− input terminal
102
, Schmitt buffers
103
and
104
, a NOR gate circuit
105
, and an SE
0
output terminal
106
. The DATA+ input terminal
101
inputs a differential data input signal DATA+. And the DATA− input terminal
102
input a differential data input signal DATA−. The two input terminals connect to the NOR gate circuit
105
through each of the Schmitt buffers
103
and
104
respectively. The outputs of the NOR gate circuit
105
is connects to the SE
0
output terminal
106
.
FIG. 2
is a timing chart on the single-end-zero receiver circuit of FIG.
1
.
FIG. 2
shows a differential data input signal DATA+ of the DATA+ input terminal
101
, a differential data input signal DATA− of the DATA− input terminal
102
, respective outputs of the Schmitt buffers
103
and
104
, and a single-end-zero signal SE
0
to be output from the SE
0
output terminal
106
.
Each of the Schmitt buffers
103
and
104
shown in
FIG. 1
has input threshold hysteresis. Therefore, as shown in
FIG. 2
, the output of the Schmitt buffer
103
varies in order at timing points a
1
, a
4
, a
5
, and a
6
with timing deviations that are based on input threshold values. Similarly, the output of the Schmitt buffer
104
varies in order at timing points a
2
and a
3
. The single-end-zero signal SE
0
is obtained by decoding the outputs of the Schmitt buffers
103
and
104
with the NOR gate circuit
105
. Therefore, glitches g
1
and g
2
occur on the SE
0
output terminal in the period between the timing points al and a
2
and the period between the timing points a
3
and a
4
, respectively.
However, the active period of the single-end-zero signal SE
0
that is actually necessary is the period between the timing points a
5
and a
6
. And the glitches g
1
and g
2
occur on the SE
0
output terminal
106
when the differential data input signals DATA+ and DATA− cross each other, as described above.
Accordingly, a certain measure against glitches needs to be taken on the input side of the single-end-zero signal SE
0
, which means a limitation on circuit designing.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a single-end-zero receiver of differential data which prevents an erroneous operation of the internal circuits due to glitches and dispenses with any circuit as a countermeasure against glitches.
The invention provides a single-end-zero receiver circuit comprising a low-value threshold detector, a high-value threshold detector, and a set/reset latch circuit.
The low-value threshold detector receives both of first and second differential data input signals and for detecting whether both of the first and second differential data input signals are lower than a first threshold voltage. The high-value threshold detector receives both of the first and second differential data input signals and for detecting whether one of the first and second differential data input signals is higher than a second threshold voltage that is higher than the first threshold voltage.
And the set/reset latch circuit outputs an SE
0
signal.
The set/reset latch circuit is set when levels of both of the first and second differential data input signals are lower than or equal to the first threshold voltage. And the set/reset latch circuit is reset when one of the levels of the first and second differential data input signals is higher than or equal to the second threshold voltage.
Each of the above components can easily be structured as a logic circuit. Since glitches are prevented from occurring on the SE
0
output terminal or in a single-end-zero signal when two differential data input signals cross each other, no glitch-induced erroneous operation occurs in the internal circuits. Further, no external circuit as a countermeasure against glitches is necessary.


REFERENCES:
patent: 5889419 (1999-03-01), Fischer et al.
patent: 5940448 (1999-08-01), Kuo
patent: 6433627 (2002-08-01), Ruesch
patent: 6462589 (2002-10-01), Taylor

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