Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2000-02-01
2001-11-27
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S020000, C257S023000, C257S024000, C257S030000
Reexamination Certificate
active
06323504
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a single-electron memory device based on the electron-hole Coulomb blockade phenomena in the parallel-coupled single-electron tunnel-junction arrays
BACKGROUND OF THE INVENTION
In order for an electron to tunnel through a single-electron tunnel-junction, the energy supplied by the voltage source should exceed the charging energy E
c
(=e
2
/C), where C is the capacitance of the tunnel-junction.
If the size of metallic islands or quantum dots comprising the tunnel-junction system becomes sufficiently small, the charging energy becomes sufficiently large accordingly, and so it is possible that the Coulomb blockade gap, where no current flows, is seen in the bias voltage region where W(=eV) is smaller than E
c
.
The single-electron device is based on the Coulomb blockade phenomena. The necessary conditions for the Coulomb blockade are that the charging energy should be much greater than the thermal energy (k
B
T) and that the junction resistance should be greater than the resistance quantum (R
K
=23.8K&OHgr;). The latter is derived from the requirement that the metallic island or quantum dot should be isolated so that the electrons are well localized both in space and time.
The fact that the size of the quantum dots is necessarily small implies possibility of high device integration. And, since only a few electrons are needed for a device operation, very low power consumption may be achieved. Therefore, research and development of the single-electron devices are actively under way in advanced countries.
As a result of the research and development, there is a paper entitled “Single Electron Tunnel Junction Array”, IEEE Transaction on Magnetics, Volume 25, Number 5, pp 1436-1439, by K. K. Likharev et al.
Also, there is a paper entitled “A Number study of the dynamics and statistics of single electron systems”, Journal of Applied Physics, Volume 78, Number 5, pp 3288-3251, by L. R. C. Fonseca et al.
Also, there is a paper entitled “Additional Coulomb Blockade and Negative Differential Conductance in Closed Two-Dimensional Tunnel Junction Arrays”, Journal of Applied Physics, Volume 84, Number 5, pp 2974-2976, by M. Shin et al.
Particularly, there have been numerous researches on single-electron memory devices, aiming at realization of ultra-high integration memory devices surpassing the physical limit of the existing silicon-based memory devices.
In the conventional memory devices, hundreds of thousands of electrons are needed to represent the binary values of 0 and 1. However, in the single-electron memory devices, only a few electrons are needed to achieve the same goal, enabling high integration and extremely low power consumption.
Among proposed single-electron memory devices making use of the Coulomb blockade phenomena, the single-electron trap consisting of the multiple tunnel-junction (MTJ) is noteworthy. The single electron trap comprises MTJ between the storage node with the self capacitance C
0
and the voltage source electrode. The number n of electrons in the storage node exhibits the bi-stable state with respect to the source-drain voltage V. The memory operation can be implemented within the hysteresis loop exhibiting the bi-stable state (for example, 0≦V≦e/C
0
).
The stored electrons can be undesirably leaked by the thermal and quantum fluctuations. To reduce the effect of the thermal fluctuations, the self capacitance of the storage node and the capacitances of MTJ should be sufficiently small (1 aF for the room-temperature operation), and the number of MTJ should be greater than 10 to effectively prevent the influence of the quantum fluctuations.
As a result of such researches, there is U.S. Pat. No. 5,844,834 entitled “Single-electron memory cell configuration”, issued on Dec. 1, 1998. Hereinafter, the afore-mentioned patent is described briefly.
In the single-electron memory device suggested in the above-mentioned patent, the single-electron tunnel-junctions showing the Coulomb blockade phenomena are arranged linearly and the storage node is attached to the end thereof. To prevent the leakage of the stored charges, the junction capacitances must be very small and a plurality of single-electron tunnel-junctions must exist between the storage node and the source electrode. Also, the single-electron transistor capable of reading the charge state in the storage node is electrically coupled to the storage node. The multiple tunnel-junction, the storage node and the single-electron transistor for reading are arranged between two electrodes so as to form a memory cell.
The charges stored in the memory node show the bi-stable state with respect to the voltage between two electrodes. A point in the hysteresis loop is designated as the read voltage and a point whose voltage is twice the read voltage is designated as the write voltage. When the voltage is varied from the read voltage to the write voltage, the zero-charge state region is passed through and, as the consequence, the charge state changes from −e to +e, enabling the write operation.
Each memory cell of an array has a single-electron transistor and a single-electron memory element. The single-electron transistor is driven by a charge stored in the memory element. When a read voltage is applied, a current flows through the single-electron transistor which is dependent on the stored charge, but the stored charge is not changed. When a write voltage is applied, the magnitude of which is greater than the read voltage, then the stored charge is changed. The memory cells of the array are each connected between the first lines and transverse second lines of a memory cell configuration.
Also, a paper entitled “single-electron memory cell”, J. Applied Physics, Volume 75m No. 10, pp 5123-5134, by K. Nakazato et al. is disclosed. Hereinafter, the single-electron memory of the above-mentioned paper will be briefly described.
In the single-electron memory suggested in the above-mentioned paper, the multiple single-electron tunnel junctions are attached to one side of the storage node and a gate electrode, where a gate voltage is applied, is attached to the other side of the storage node. An electrometer, which is a single-electron transistor, is also weakly coupled to the storage node to read its charge state.
The charge state of the storage node shows bi-stability with respect to the gate voltage, and as the consequence, the voltage of the storage node exhibits the hysteresis loop with respect to the gate voltage. The hysteresis loop contains two internal values, low and high values, which can be designated to represent the memory state of 0 and 1, respectively. The number of electrons involved to represent the high and low values are approximately 40 and they are very sensitive to the number of MTJs and the capacitance of the tunnel-junctions.
The basic memory operation is described in terms of the classical single-electron tunneling theory, where the Coulomb blockade and the free energy change by single-electron tunneling are considered. As electrons are transferred to the storage node one by one, the potential barrier builds up in the MTJ region and therefore the transferred electrons are trapped in the storage node.
An experimental memory circuit was fabricated using side-gated constrictions in &dgr;-doped GaAs and the basic operation was confirmed from 30 mK up to liquid-helium temperature of 4.2 K in the above-mentioned paper. This memory can store information for longer than several hours. The intrinsic single-electron memory characteristics in a regime where cotunneling is neglected are investigated, and the overall characteristics are explained by a semiclassical model.
Also, a paper entitled “Single-Electron Traps: A Quantitative Comparison of Theory and Experiment”, Journal of Applied Physics, Volume 81, Number 5, pp 2269-2281, by K. A. Matsuoka proposed the single-electron memory device. Hereinafter, the single-electron memory in the above-mentioned paper will be briefly described.
The single-electron memory device of the above-m
Lee Seong Jae
Park Kyoung Wan
Shin Min Cheol
Crane Sara
Electronics and Telecommunications Research Institute
Seed IP Law Group PLLC
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