Single cycle store operations in a virtual memory

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G06F 900, G06F 930, G06F 938, G06F 906

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active

047978171

ABSTRACT:
A device is described by this disclosure for performing memory stores in a memory of a computer system. The computer system includes a processor having a pipeline for processing commands in multiple stages; wherein the commands include a plurality of instructions, including store instructions, and virtual addresses. When the processor processes a store command, the pipeline is blocked until the associated virtual address is translated by a translation device to a real address. In the present device, if a selected store operation is processed, a check is made to see if the associated virtual address has previously been translated, and if it has, the pipeline is unblocked, thus enhancing the processing of store operations.

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