Single cycle dispatch delay in a multiple instruction dispatch m

Details Single cycle dispatch delay in a multiple instruction dispatch m Single cycle dispatch delay in a multiple instruction dispatch m

1994-11-14

1995-12-26

Treat, William M.

395800, G06F 938

Patent

active

054796229

ABSTRACT:
A data processing system including a circuit for storing a plurality of instructions in a sequence together with a circuit for fetching a plurality of instructions. A circuit is provided for dispatching a plurality of the instructions to one or more processors for execution during a single computation cycle. A control circuit is connected to the dispatching circuit to delay the dispatching of an instruction. when the instruction has an execution result that is dependent upon a previous instruction execution that will set at least one bit in a condition register. The delayed instruction is delayed until that condition register has been accordingly set.

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