Stock material or miscellaneous articles – Circular sheet or circular blank
Reexamination Certificate
1999-10-28
2002-05-14
Copenheaver, Blaine (Department: 1771)
Stock material or miscellaneous articles
Circular sheet or circular blank
C117S019000, C117S013000, C117S021000, C117S036000, C117S020000, C117S917000
Reexamination Certificate
active
06387466
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a single-crystal silicon wafer for semiconductor device produced by the so-called CZ method, the Czochralski method, in which silicon is melted in a crucible and single-crystal silicon is pulled, more specifically, to a silicon wafer of large diameter and high quality optimal for producing an ultra highly integrated device.
2. Description of the Related Art
Conventionally, a single-crystal silicon substrate processed from a single-crystal silicon and used for a semiconductor device of which the scale of integration is ever enlarging and accordingly the more minute design rules is being required has been manufactured by the Czochralski method (CZ method) which is advantageous for obtaining a large diameter silicon wafer. Especially, the scale of integration of a DRAM increases by four times and the size of a chip by one and a half times every three years. Therefore, a wafer of larger diameter is required in addition of more minute design rules to evade the reduction in chip yields per wafer and reduce the chip cost.
To meet the demand for larger chip size, single-crystal silicon wafers of large diameter of 300 mm are required (NIKKEI MICRODEVICES, November 1992) and at the same time improvements in surface flatness and surface roughness and reductions in heavy metal impurities, micro defects, and/or foreign matters on the surface are required.
Micro defects and foreign matters on the surface of a wafer can be detected together optically and these are grasped as particles and considered as an extremely important factor for quality design.
It is required for a wafer of diameter of 300 mm for a semiconductor device with 0.18 &mgr;m design rules to reduce the number of particles of 0.09 &mgr;m and larger in size detected optically to 100 and smaller. A semiconductor device undergoes multiple manufacturing processes and monitoring of adherence of particles and heavy metal impurities is necessary in process control. A single-crystal silicon of extremely low particle level is necessary as process monitor.
For the realization of particle level reduction necessitated as mentioned above, reduction in the particles ascribable to crystal, which particles are micro defects formed due to thermal history in the manufacturing process of single-crystal silicon, is an important problem to be challenged.
When a silicon wafer sliced from a single-crystal silicon ingot is cleaned with ammonia based cleaning and/or in the process afterward, there develop on the wafer etch pits and these pits will be detected optically as particles and also induce problems in the process making device as so-called particles.
These particles are generated owing to thermal condition and others in pulling the crystal and are called COP or Crystal Originated Particles (Jpn. J. Appl. Phys. 29(1990)L1947-L1949).
Furthermore, although measures are taken for prevention of micro defects due to processing in the mirror-polishing process of the surface of a wafer and of adherence of minute foreign matter and/or impurities in the processes afterward, yet it has not been possible to reduce the number of particles of 0.09 &mgr;m and larger in size to 100 and smaller by conventional arts.
Main manufacturing processes relating to quality factors required from the market of silicon wafer as mentioned above are as diverse as the pulling process of crystal in the case of larger diameter of silicon ingot; slicing, lapping, and polishing processes in relation to flatness; etching and polishing processes in relation to surface roughness; crystal pulling, slicing, lapping, polishing, and cleaning process in relation to defects on the surface including particle problem; and crystal pulling, slicing, lapping, polishing, and cleaning processes in relation to contamination of the surface, especially contamination with heavy metals.
About the particle problem on the surface, solution of which is the object of the present invention, there are cause ascribable to crystal and cause ascribable to the processing of a wafer, as mentioned above to some extent. Although reduction of particles ascribable to the processing of a wafer is extremely important and the study for its improvement has been considered as a matter of course, reduction of defects in a single-crystal, as raw material, is fundamentally important for the reduction of particles. Unless this reduction is not achieved, the object cannot be attained even by how much processes afterward are improved.
Until now, a way to find a breakthrough to reduce the particles ascribed to crystal has not been found, and no clue to solve the problem has been obtained.
SUMMARY OF THE INVENTION
The present invention aims, mainly by paying attention to the particles ascribed to crystal, to obtain a high quality silicon wafer of large diameter optimal to manufacture an ultra highly integrated device.
The present invention provides a silicon wafer of diameter of 300 mm and larger sliced from a single-crystal silicon ingot pulled by CZ method, on the main surface of which wafer are detected 120 and smaller number of particles of 0.083 &mgr;m and larger in size and/or 80 and smaller number of particles of 0.09 &mgr;m and larger in size after mirror-polished and cleaned with ammonia based cleaning solution.
As mentioned above, the limit number of particles on the surface of a wafer is determined by the design quality specification taking into consideration the processes afterward, and with 0.18 &mgr;m design rules (line width of circuit pattern on a device) the number of particles of 0.09 &mgr;m and larger is in size required to be equal to or smaller than 100 per wafer.
The number of particles per chip differs according to individual device. For example, in the case of a DRAM with 0.18 &mgr;m design rules, about 400 IC chips are obtained from a wafer of a diameter of 300 mm, and to secure the desired IC chip yields the number of particle of 0.090 &mgr;m and larger in size is required to be 0.2~0.3 or smaller per chip.
Conspicuous improvement in chip yields can be expected by the reduction of particles on a wafer.
As there are, as mentioned above, two groups of factors which effect particles, it is necessary for clarification of the result of improvement in the number of particles ascribable to crystal, which improvement is the main object of the present invention, to investigate the influence of affecting group of factors independently. The most desirable method is to separately detect the particles due to both factors and obtain each number of particles, which is impossible with the present technology.
The present invention provides a way for determining the effect of improvement in crystal, in which the standard method which has reached a state of practicability in processing a silicon ingot of large diameter is defined so that the number of particles due to the processing is a certain stable value. Wafers processed by said standard method and having a certain stable number of particles due to the processing and some unknown number of particles ascribable to the crystal are detected to obtain the sum of the number of these particles.
Current manufacturing method of a semiconductor wafer comprises; slicing process in which a single-crystal ingot pulled by the pulling apparatus of the Czochralski method is sliced to obtain thin disk-like wafers; chamfering process in which the edges of the periphery of the sliced wafer are chamfered to prevent from chipping and/or cracking; lapping process in which the main surface of the chamfered wafer is flattened; wet etching process in which the residual process damage layer due to chamfering and lapping is removed; mirror-polishing process in which the main surface and the chamfered portion of the etched wafer is mirror-polished; and cleaning process in which polishing agent and foreign matter remaining on the polished wafer are removed to secure good cleanliness.
A variety of developments have been made to attain improvement concerning quality items in these processes such as flatness
Fusegawa Izumi
Sato Masakazu
Copenheaver Blaine
Crowell & Moring LLP
Shin-Etsu Handotai & Co., Ltd.
Vo Hai
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