Single counter for controlling multiple finite state...

Details Single counter for controlling multiple finite state... Single counter for controlling multiple finite state...

1998-05-13

2001-06-26

Chin, Wellington (Department: 2664)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C709S228000

Reexamination Certificate

active

06252879

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a multi-port bridge for a local area network. More particularly, the invention relates to a single counter for controlling multiple finite state machines in a multi-port bridge for a local area network.
BACKGROUND OF THE INVENTION
Nodes of a local area network (LAN) are typically interconnected by a shared transmission medium. The amount of data traffic that the shared transmission medium can accommodate, however, is limited. For example, only one node at a time can successfully transmit data to another node over the shared transmission medium. If two or more nodes simultaneously attempt to transmit data, a data collision occurs, which tends to corrupt the data being transmitted. Thus, nodes that share a transmission medium are considered to be in a same collision domain.
A multi-port bridge allows simultaneous communication between nodes of the LAN by segmenting the LAN into multiple collision domains (also referred to as network segments), each segment having a corresponding transmission medium.
FIG. 1
illustrates a conventional local area network (LAN) including a multi-port bridge
20
. The multi-port bridge
20
in this example has eight ports A-H, though the number of ports can vary. Each port A-H is connected to a segment
21
-
28
of the LAN. Each segment
21
-
28
typically includes one or more nodes
29
-
44
, such as a workstation, a personal computer, a data terminal, a file server, a printer, a facsimile, a scanner or other conventional digital device. Each of the nodes
29
-
44
has an associated node address which uniquely identifies the node. The nodes
29
-
44
are configured to send data, one to another.
When the LAN operates according to Ethernet standards, such as the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standard, data is communicated in the form of discrete packets.
FIG. 2
illustrates a conventional IEEE 802.3 data packet
50
. The data packet
50
has an eight byte long pre-amble
51
which is generally utilized for synchronizing a receiver to the data packet
50
. The pre-amble
51
includes seven bytes of pre-amble and one bite of start-of-frame. Following the pre-amble
51
, the data packet
50
includes a six byte long destination address
52
, which is the node address of a node which is an intended recipient for the data packet
50
. Next, the data packet
50
includes a six byte long source address
53
, which is the node address of a node which originated the data packet
50
. Then, following the source address
53
is a two-byte data type field
54
. Following the data type field
54
is a data field
55
. The data field
55
can be up to 1500 bytes long. In addition, the packet can include a two-byte length field between the source address
53
and data type field
54
. Finally, the data packet
50
includes a four-byte frame check field
56
which allows a recipient of the data packet
50
to determine whether an error has occurred during transmission of the data packet
50
.
When a node (source node) sends data to another node (destination node) located on its same segment of the LAN (intra-segment communication), the data is communicated directly between the nodes without intervention by the multi-port bridge
20
and is known as an intra-segment packet. Therefore, when the multi-port bridge
20
receives an intra-segment packet, the multi-port bridge
20
does not bridge the packet (the packet is filtered). When a node (source node) sends a data packet to another node (destination node) located on a different segment (inter-segment communication), the multi-port bridge
20
appropriately forwards the data packet to the destination node.
Accordingly, each port A-H of the multi-port bridge
20
receives packets from the network segment associated with the port, forwards the packets that are to be transmitted by another port, and also transmits packets to the network segment associated with the port. To achieve each of these functions, each port conventionally includes relatively complex circuitry, such as a micro-processor and its associated circuitry. This tends to result in production costs for such a multi-port bridge
20
that are higher than desired and also tends to result in the performance and reliability of the multi-port bridge
20
being lower than desired. Because the multi-port bridge
20
includes a plurality of ports, the complexity of each port is multiplied by the number of ports, thereby, exacerbating these problems.
Therefore, what is needed is improved technique for reducing the complexity of the ports in a multi-port bridge. Preferably, such an improved technique would enhance, rather than sacrifice, functionality and performance of the ports.
SUMMARY OF THE INVENTION
The invention is a technique for achieving a single counter in each port of a multi-port bridge for a local area network where the single counter is utilized for controlling multiple finite state machines in the port. The multi-port bridge includes a switch engine, a memory and a plurality of ports, all of which are interconnected by a high speed communication bus. The switch engine includes a bus controller, a memory controller and a look-up controller, each preferably being a finite state machine. The memory controller provides an interface between the memory and the communication bus. The bus controller controls access to the communication bus by collecting requests and granting the requests in an appropriate priority. The look-up controller determines to which port each packet is to be directed based upon the destination node address for the packet.
The high speed communication bus includes bit lines dedicated to communicating control commands, bit-lines dedicated to communicating data, and several bit-lines having special purposes. For example, two bit-lines are preferably dedicated to initiating access to the bus, each having a respective priority, another bit-line is dedicated to jam requests (for applying backpressure), still another bit-line is dedicated to the memory controller and yet another bit-line is dedicated to providing a bus clock signal. The memory includes look-up tables utilized for appropriately directing data packets among the ports, packet buffers utilized for temporarily storing packets and mailboxes for providing an interface between the switch engine and an external processor.
Each port includes a port controller having a memory pointer finite state machine (FSM), a MAC transceiver, receive FSM, a transmit FSM, a receive buffer, a transmit buffer and a memory pointer buffer. Packets received from a LAN segment by the transceiver are directed to the communication bus through the receive buffer, while packets to be transmitted over the LAN segment are directed to the transceiver through the transmit buffer. The memory pointer buffer stores memory pointers in a queue for transmission by the port, one memory pointer for each data packet being stored in the packet buffers of the memory. The memory pointer includes an address assigned to the packet in the memory.
Each of the transmit FSM, memory pointer FSM and receive FSM requires a set of registers, such as a counter for keeping track of the current state of the FSM and registers for storing parameters utilized by the FSM. At any time, none, one, two or all of the FSMs in a port can be active. At least one register is identified that is used only in certain states in each of the FSMs such that no more than one FSM requires use of this register at the same time. This register, therefore, is shared by multiple FSMs, though preferably more than one register is shared in this manner.
An advantage of this technique of the present invention is that it reduces the number of registers required for each port, thus, reducing the cost of producing the multi-port bridge. Because the multi-port bridge according to the present invention preferably has twenty-six ports, the advantages are substantial.


REFERENCES:
patent: 5517494 (1996-05-01), Green
patent: 5559796 (1996-09-01), Edem et al.
patent: 5680622 (1997-10-01), E

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