Single clocked latch circuit

Details Single clocked latch circuit Single clocked latch circuit

1983-11-25

1986-02-11

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 307272A, 307291, 307480, H03K 3037

Patent

active

045700826

ABSTRACT:
An edge triggered polarity hold, clocked latch circuit is disclosed which requires the use of only a single clock line for operation. The latch circuit comprises three set-reset type latches. Each of two latches receives one set and one reset signal. The third latch receives two reset signals and one set signal. A single clock signal is applied jointly to a reset terminal of the third latch and of one of the first two latches. A data signal is applied to the set terminal of the third latch. The other of the first two latches constitutes the output latch and is connected to receive the outputs of the remaining latches. The output latch produces an output equal to an input data signal upon each occurrence of the leading edge of an input clock signal. The output is held (latched) until the occurrence of the next clock signal when the output becomes equal to the then existing input data signal.

REFERENCES:
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patent: 3740590 (1973-06-01), Hart et al.
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Hart et al., "Latch Circuit", IBM Tech. Disc. Bull., vol. 15, No. 1, Jun. 1972, p. 203.
Bodner, "100% Testable D-Type Flip-Flop", IBM Tech. Disc. Bull., vol. 15, No. 9, Jan. 1973, pp. 2487-2488.

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