Coded data generation or conversion – Digital code to digital code converters – To or from packed format
Reexamination Certificate
2001-07-25
2002-10-29
JeanPierre, Peguy (Department: 2879)
Coded data generation or conversion
Digital code to digital code converters
To or from packed format
C360S051000, C360S048000, C360S018000, C370S468000
Reexamination Certificate
active
06473007
ABSTRACT:
The present invention relates to the generation of digital video signals. In particular, the invention is directed to improvements to Asynchronous Serial Interface (ASI) bitstream formation in order to simplify the design requirements of a downstream receiver, especially by lowering the required processing speed.
The Moving Picture Experts Group (MPEG) created the ISO/IEC international Standards 11172 and 13818 (generally referred to as MPEG-1 and MPEG-2 format respectively) to establish a standard for coding/decoding strategies. Although these MPEG standards specify a general coding methodology and syntax for generating an MPEG compliant bitstream, many variations and preconditions are permitted.
The locked clock approach facilitates the formation of various output format standards. In the particular case of ASI output, a logic circuit uses the 27 Mhz to generate the data clock for inputting data to an ASI formatting chip set. The DVB-ASI format specifies a data rate of 27 Mbytes/sec, and allows for insertion of specially defined idle characters both between transport packets and within transport packets.
It is possible to map the ATSC byte rate to this interface rate by only inserting the special idle characters between packets. Prior to the initiation of the packet data output by the Transport Stream Encoder (TSE) Software, special idle characters are continuously output. After the Transport packet data output is initiated, the Output Interface format is a flow of 188 packet bytes followed by a string of the special idle characters before the next Transport packet bytes are issued. This forms an ASI Packet. The invention encompasses alternate systems and methods for implementing a locked clock approach.
SUMMARY OF THE INVENTION
The invention relates to a system and method for generating a transport packet stream. The invention encompasses outputting an ASI group having a plurality of short and long ASI packets in a fixed sequence, wherein each short and long ASI packet each has an associated transport packet and a fixed number of special idle characters and wherein the transport packets are dispersed among the special idle characters.
In one embodiment, the transport packets have a plurality of adjacent bytes interleaved among special idle characters. In another embodiment, the transport packets have a plurality of separate bytes that are interleaved among the special idle characters. In yet another embodiment, 10 special idle characters are interleaved between successive transport packets bytes.
The invention encompasses systems and methods for generating a transport packet stream wherein the short ASI packet has 2093 bytes formatted with a 188 byte transport packet wherein 10 special idle characters are interleaved between successive transport packets bytes followed by 25 special idle characters.
The invention encompasses systems and methods for generating a transport packet stream wherein the long ASI packet has 2094 bytes formatted with a 188 byte transport packet wherein 10 special idle characters are interleaved between successive transport packets bytes followed by 26 special idle characters.
The invention encompasses outputting an ASI group having a plurality of short and long ASI packets in a fixed sequence, wherein the short ASI packets each have 2093 bytes including a 188 byte transport packet and 1905 special idle characters and wherein the long ASI packets each have 2094 bytes including a 188 byte transport packet and 1906 special idle characters and wherein the transport packets are dispersed among the special idle characters. Again, the transport packet bytes can be a unified group interleaved among special idle characters or the transport packets bytes can be separately interleaved among the special idle characters.
REFERENCES:
patent: 4736371 (1988-04-01), Tejima et al.
patent: 5619337 (1997-04-01), Naimpally
patent: 5990967 (1999-11-01), Kawakami et al.
patent: 6097739 (2000-08-01), Yamashita
patent: 6157674 (2000-12-01), Oda et al.
patent: 6233256 (2001-05-01), Dieterich et al.
patent: 6246701 (2001-06-01), Slattery
patent: 6351474 (2002-02-01), Robinett et al.
Acampora Alfonse A.
Beltz John P.
Lyons Paul W.
Dechert
Goldberg Daniel S.
Jean-Pierre Peguy
Leitch Incorporated
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