Single clock memory having a page mode

Details Single clock memory having a page mode Single clock memory having a page mode

1994-03-21

1995-04-25

Popek, Joseph A.

Static information storage and retrieval

Addressing

Byte or page addressing

354233, 354235, G11C 800

Patent

active

054105145

ABSTRACT:
The present invention realizes page mode memory access in a single clock memory. A control signal PAGE, one level of which designates an ordinary mode and the other level of which designates a page mode, is provided to a single clock memory from the outside. A mode state identification circuit identifies four mode states, ordinary mode, page-in, during-page, and page-out, by decoding the combination of the control signal levels in two consecutive memory cycles. A memory control circuit part of a memory array is thereby controlled based on the result of the identification.

REFERENCES:
patent: 4625870 (1987-06-01), Kumanoya et al.
patent: 4685084 (1987-08-01), Canepa
patent: 4750839 (1988-06-01), Wang et al.
patent: 4789966 (1988-12-01), Ozaki
patent: 4833650 (1989-05-01), Hirayama et al.
patent: 4876671 (1989-10-01), Norwood et al.
patent: 4970418 (1990-11-01), Masterson

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