Single circuit for detecting a frame synchronization pattern and

Details Single circuit for detecting a frame synchronization pattern and Single circuit for detecting a frame synchronization pattern and

1990-03-01

1991-10-15

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

3701054, H04L 704

Patent

active

050581414

ABSTRACT:
A single circuit for detecting a synchronization pattern in a serial data stream. Subsequent to detecting the synchronization pattern, the single circuit generates the control signals for converting the serial data to a parallel format and loading the parallel data into a first-in-first-out (FIFO) memory. The single circuit includes a controller arranged to receive the serial data stream. A counter is connected to the controller. When the counter is detecting the synchronization pattern and the synchronization pattern is being received, the counter is incremented. Absent the synchronization pattern being received, the counter is reset to a predetermined starting point. Subsequent to detecting the synchronization pattern, the counter generates a load signal. The single circuit further includes a pulse generator arranged to receive the load signal from the counter and generate a pulse of duration equal to a bit period of the serial data stream. An indicator is provided which generates an in-synch signal after the counter detects the synchronization pattern.

REFERENCES:
patent: 4607378 (1986-08-01), Catlin et al.
patent: 4740962 (1988-04-01), Kish, III
patent: 4787095 (1988-11-01), Forth et al.
patent: 4794626 (1988-12-01), Tanabe et al.

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