Single chip temperature compensated reference diode and method f

Details Single chip temperature compensated reference diode and method f Single chip temperature compensated reference diode and method f

1975-11-25

1978-02-21

Larkins, William D.

357 28, 357 33, 357 40, 357 52, 357 76, 357 89, H01L 2990

Patent

active

040756491

ABSTRACT:
A reference diode and a method for making same are described, wherein a single wafer of semiconductive material is processed to provide a reverse PN junction acting in its breakdown region and to provide one or more forward PN junctions in electrical series with the reverse junction. A wafer of semiconductive material of one conductivity type is diffused with an impurity to form a plurality of regions of semiconductive material of opposite conductivity type. The regions are laterally displaced from each other and each forms a reverse PN junction at the interface between the region and the remainder of the wafer. An impurity is then diffused into one or more of these regions to form one or more forward PN junctions. An additional reverse PN junction is then formed between and adjacent to two of the previously formed regions. The latter reverse PN junction is formed by alloying or diffusing an impurity into the wafer to provide a region of opposite conductivity type having a higher conductivity than the adjacent regions. The reverse PN junction thus formed by the latter step exhibits a lower breakdown voltage than the adjacent reverse PN junctions. All exposed PN junctions extend to only one surface of the wafer and are passivated. Metal contact pads are then deposited on the opposing faces of the wafer to permit axial connections to the temperature compensated diode.

REFERENCES:
patent: 3567965 (1971-03-01), Weinerth
patent: 3574009 (1971-04-01), Chizinsky et al.
patent: 3739238 (1973-06-01), Hara

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