Single-chip synchronous dynamic random access memory (DRAM) syst

Details Single-chip synchronous dynamic random access memory (DRAM) syst Single-chip synchronous dynamic random access memory (DRAM) syst

1997-07-10

1998-12-22

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

36523003, 36523006, G11C 800

Patent

active

058525866

ABSTRACT:
To obtain high access speed regardless of a structure and operating characteristics of an external central processing unit (CPU), a synchronous dynamic random access memory (DRAM) system includes first and second DRAM cell arrays, and a first address generator for outputting a first address and a second address respectively to the first and second DRAM cell arrays simultaneously in a first mode. In a second mode, the first address generator outputs the first address and the second address respectively to the first and second DRAM cell arrays sequentially.

REFERENCES:
patent: 5587962 (1996-12-01), Hashimoto et al.
patent: 5594702 (1997-01-01), Wakeman et al.
patent: 5600606 (1997-02-01), Rao
patent: 5652733 (1997-07-01), Chen et al.
patent: 5717651 (1998-02-01), Kikukawa et al.
patent: 5751656 (1998-05-01), Schaefer

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