Single chip microcomputer with external decoder and memory and i

Details Single chip microcomputer with external decoder and memory and i Single chip microcomputer with external decoder and memory and i

1981-09-23

1984-05-22

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1300

Patent

active

044505248

ABSTRACT:
A data processor system having a total memory capacity, an integrated circuit chip having thereon a central processing unit (CPU), a ROM, a RAM, a first decoder responsive to addresses supplied thereto for determining the location of the RAM in the total memory capacity, and logic for disabling the ROM from the CPU and for relocating the RAM in the total memory capacity. Also provided are a generator for generating a first control signal having first and second states, first gating logic responsive to the first state of the control signal to disable the ROM and to disconnect the output of the first decoder from the RAM. Further provided is an adjustable second decoder positioned externally of the chip and responsive to addresses supplied thereto from the CPU to generate an output signal defining a selectable location of the RAM in the total memory capacity, and second gating logic responsive to the first state of the control signal to connect the output signal of the adjustable second decoder to the RAM to thereby define the selectable location of the RAM in the total memory capacity.

REFERENCES:
patent: 3693159 (1972-09-01), Hilberg
patent: 3771143 (1973-11-01), Taylor
patent: 3781826 (1973-12-01), Beausoleil
patent: 3813650 (1974-05-01), Hunter
patent: 3845476 (1974-10-01), Boehm
patent: 3882470 (1975-05-01), Hunter
patent: 3897626 (1975-08-01), Beausoleil
patent: 3917933 (1975-11-01), Scheuneman
patent: 3934227 (1976-01-01), Worst
patent: 4047163 (1977-09-01), Choate et al.
patent: 4051460 (1977-09-01), Yamada et al.
patent: 4112502 (1978-09-01), Scheuneman
patent: 4153933 (1979-05-01), Blume, Jr. et al.

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