Single-chip memory system having a decoder for pulse word line m

Details Single-chip memory system having a decoder for pulse word line m Single-chip memory system having a decoder for pulse word line m

1997-02-20

1999-11-02

Cabeca, John W.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518911, 365226, 711150, G11C 800

Patent

active

059783087

ABSTRACT:
To avoid selecting multiple word lines, a memory system including a pulse word line method capability includes a decoder for activating one word line when a clock signal has an active level and for forcibly inactivating all word lines when the clock signal has an inactive level.

REFERENCES:
patent: 5507024 (1996-04-01), Richards, Jr.
patent: 5577003 (1996-11-01), Fuji
patent: 5610872 (1997-03-01), Toda
patent: 5612917 (1997-03-01), Kozaru et al.
patent: 5666324 (1997-09-01), Kosugi et al.
patent: 5673225 (1997-09-01), Jeong et al.
patent: 5768203 (1998-06-01), Fuji

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