Single chip frame buffer and graphics accelerator

Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit

Reissue Patent

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C345S501000, C345S545000, C345S567000

Reissue Patent

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RE040326

ABSTRACT:
A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.

REFERENCES:
patent: 4646151 (1987-02-01), Welles et al.
patent: 4691295 (1987-09-01), Erwin
patent: 4740782 (1988-04-01), Aoki et al.
patent: 4918526 (1990-04-01), Lewis et al.
patent: 5027212 (1991-06-01), Marlton et al.
patent: 5083047 (1992-01-01), Horie
patent: 5144223 (1992-09-01), Gillingham
patent: 5170154 (1992-12-01), Mantopoulos
patent: 5198708 (1993-03-01), Gillingham
patent: 5267201 (1993-11-01), Foss et al.
patent: 5283761 (1994-02-01), Gillingham
patent: 5305283 (1994-04-01), Simokura et al.
patent: 5392391 (1995-02-01), Caulk et al.
patent: 5406523 (1995-04-01), Foss et al.
patent: 5414662 (1995-05-01), Foss et al.
patent: 5442748 (1995-08-01), Chang et al.
patent: 5448733 (1995-09-01), Satoh et al.
patent: 5469401 (1995-11-01), Gillingham
patent: 5572655 (1996-11-01), Tuljapurkar et al.
patent: 5712664 (1998-01-01), Reddy
patent: 3628286 (1998-02-01), None
patent: 0 165 441 (1985-12-01), None
patent: 0334524 (1989-09-01), None
patent: 0 383 080 (1990-08-01), None
patent: 0 474 366 (1992-03-01), None
patent: 0 492 840 (1992-07-01), None
patent: 0 547 892 (1993-06-01), None
patent: 0 260 578 (1998-03-01), None
patent: 2 217 066 (1987-10-01), None
patent: 2 208 344 (1989-03-01), None
“The integrated display controller (IDC) for VLSI design workstation” by Jurgen Stark, Computer & Graphics vol. 11, No. 2, pp. 185-192, 1987.
“100 Mpixel/sec single chip integrated graphics controller (IGC)” by D. Mansharamani et al, IEEE 1991, Custom Integrated Circuits Conf, May 12-15, 1991, pp. 16.5.1-16.5.4.
NEC Research and DEvelopment, vol. 33, No. 4, Oct. 1992, Tokyo, JP, pp. 585-594 “Integrated Memory Array Processor”.
IEEE Journal of Solid-State Circuits, vol. 25, No. 1, Feb. 1990, N.Y., pp. 30-35, A 50 MHz 8Mbit Video Ram with a Column Direction Drive Sense Amplifier.
Proceedings of IEEE 1991 Custom Integrated Circuit Conference. D. Mansharamani et al 100Mpixel/sec Single Chip Integrated Graphics Controller, p. 16.51-16.54, May 12-15, 1991.

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