Single chip frame buffer and graphics accelerator

Details Single chip frame buffer and graphics accelerator Single chip frame buffer and graphics accelerator

1994-06-02

1997-12-02

Powell, Mark R.

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

395501, 395509, 395521, G09G 500

Patent

active

056941439

ABSTRACT:
A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.

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