Single chip controller-memory device with interbank cell replace

Details Single chip controller-memory device with interbank cell replace Single chip controller-memory device with interbank cell replace

1996-02-01

1997-12-23

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

365200, 36523006, 371 102, G11C 800

Patent

active

057012709

ABSTRACT:
A memory subsystem 300 including processing circuitry 103 and first and second banks of memory 200/201. Each bank 200/201 includes a predetermined number of primary memory cells 200 and a predetermined number of redundant memory cells 205. An address bus 202 allows processing circuitry 103 to address at least one of the primary cells 200. The redundancy bus 301 allows processing circuitry 103 to address at least one of the redundancy cells 205.

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"A Distributed Globally Replaceable Redundancy Scheme for Sub-Half-Micron VLSI Memories and Beyond" by Yagamara, Saito, Fujita, Nishimura & Anami, IEEE Journal of Solid State Circuits vol. 31, No. 2, Feb. 1996 pp. 195-201 .

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