Single chip CMOS transmitter/receiver and method of using same

Details Single chip CMOS transmitter/receiver and method of using same Single chip CMOS transmitter/receiver and method of using same

2002-09-25

2004-08-24

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C455S226200, C455S217000, C375S345000

Reexamination Certificate

active

06781424

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a communication system, and in particular, to a CMOS radio frequency (RF) communication system.
2. Background of the Related Art
Presently, a radio frequency (RF) communications system has a variety of applications including PCS communication and IMT systems. As such, a CMOS chip integration of the system has been pursued to reduce the cost, size and power consumption.
Generally, the RF communication system is composed of RF front-end block and base-band digital signal processing (DSP) block or baseband modem block. Currently, the base-band DSP block can be implemented with low cost and low power CMOS technology. However, the RF front-end cannot be implemented by CMOS technology because of limitations in speed, bandwidth and noise characteristics, which are below the speed, the frequency and noise specifications of popular RF communication systems.
For example, the PCS hand-phone systems operate at a frequency over 2.0 GHz, but current CMOS technology reliably operates only up to approximately 1.0 GHz in terms of speed and noise. Hence, the RF front-end block is implemented using bipolar, bi-CMOS or GaAs technology that has better speed, bandwidth and noise characteristics than CMOS technology but is more expensive and consumes more power.
Currently, two different types of RF architecture called “direct conversion” and super-heterodyne (double conversion) are used for CMOS RF communication systems. Both architectures have advantages and disadvantages in terms of CMOS implementations.
FIG. 1
is a diagram showing a related art direct conversion RF system
100
. A related art direct conversion CMOS RF communication system
100
includes an antenna
105
, a RF filter
110
, a low noise amplifier (LNA)
120
, a phase-locked loop (PLL)
130
, a first mixer
140
, a second mixer
142
, first and second amplifiers
150
,
152
, a first low pass filter (LPF)
160
, a second LPF
162
, first and second variable gain amplifiers (VGA)
170
,
172
each including automatic gain control (AGC) loops, a first analog/digital (A/D) converter
180
, a second A/D converter
182
, a third mixer
190
and a power amplifier
192
.
The antenna
105
receives RF signals. The received RF signal is composed of various RF bands. Selected RF signals are then filtered at the RF filter
110
. That is, out-of-band RF signals (e.g., irrelevant RF bands) are removed by the RF filter
110
. The filtered in-band RF signals are amplified with a gain at the LNA
120
. However, the in-band RF signal is composed of in-band channels and possible image bands, which is shown as A in
FIGS. 1 and 2
. The in-band RF signals passing through the LNA
120
are directly demodulated into base band signals by quadrature multiplication at the first and second mixers
140
and
142
because the LO frequency is equal to the carrier frequency. The PLL
130
preferably generates two types of clock signals, I clock signals and Q clock signals using a voltage controlled oscillator (VCO). The I clock signals and the Q clock signals are the same excepting a phase difference. The I signals preferably have a phase difference of 90 degrees from the Q signals. That is, Q signals are phase shifted with respect to quadrature phase shift I signals. The two sets of signals I and Q are preferably used to increase the ability of the RF system to identify or maintain received information regardless of noise and interference. Sending two types of signals having different phases reduces the probability of information loss or change.
As shown at B in
FIGS. 1 and 2
, the down converted signal includes the desired channel, adjacent channels and an up-converted signal. The down-converted signal is amplified by amplifiers
150
,
152
before passing through corresponding low-pass filters (LPF)
160
,
162
to prevent drastic signal-to-noise-ratio (SNR) degradation by noise injection from the LPFs
160
,
162
, which is shown as C in
FIGS. 1 and 2
. The signals from the LPFs
160
,
162
are amplified by variable gain amplifiers (VGAs)
170
,
172
, respectively, and become respective signals required for A/D conversion at first and second A/D converters
180
,
182
. However, the desired channel cannot be amplified to a maximum level allowed by the linearity limit because the adjacent channel can reach the linearity limit before the desired channel is amplified to the required level. Thus, in the related art direct conversion architecture
100
, amplification of the entire channel is reduced as the adjacent channel power increases, which also results in SNR degradation. As shown at D in
FIGS. 1 and 2
, the LPFs
160
,
162
output a large noise floor that is added to the desired channel by the LPFs
160
,
162
. Accordingly, both the desired channel and the noise floor are amplified when the desired channel is amplified to the required level before the A/D conversion as shown at E in
FIGS. 1 and 2
.
The digital signals are then transferred to a base-band discrete-time signal processing (DSP) block (not shown). Channel selection is performed by changing frequency f
0
in at the phase-locked loop (PLL)
130
.
As described above, the related art direct conversion RF system
100
has advantages for CMOS RF integration because of its simplicity. In the related art direct conversion RF system only a single PLL is required. Further, in the related art direct conversion RF system high-quality filters are not required. However, the related art direct conversion architecture has disadvantages that make single chip integration difficult or impossible. As shown in
FIG. 3A
, clock signals cos &ohgr;
LO
t from a local oscillator (LO) such as the VCO may leak to either the mixer input or to the antenna where radiations can occur because the local oscillator (LO) is at the same frequency as the RF carriers. The unintentionally transmitted clock signals &Dgr;(t) cos &ohgr;
LO
t can reflect off nearby objects and be “re-received” by the mixer again. The low pass filter outputs a signal M(t)+&Dgr;(t) because of leakages of clock signals. As shown in
FIG. 3B
, self-mixing with the local oscillator results in problems such as time variations or “wandering” DC-offsets at the output of the mixer. The time-varying DC-offset together with inherent circuit offsets significantly reduce the dynamic range of the receiver portion. Further, as discussed above, a related art direct conversion RF system requires a high-frequency, low-phase-noise PLL for channel selection, which is difficult to achieve with an integrated CMOS voltage controlled oscillator (VCO).
FIG. 4
shows a block diagram of a related art RF communication system
400
according to a double conversion architecture that considers all of the potential channels and frequency translates them first from RF to IF and then from IF to baseband using a tunable channel select PLL. As shown in
FIG. 4
, the RF communication system
400
includes antenna
405
, a RF filter
410
, a LNA
420
, IR filter
425
, a phase lock loop (PLL) PLL
1
430
, a first mixer
435
, a IF filter
440
, IF VGA
450
, a PLL
2
460
, a second mixer
465
, a LPF
470
, an A/D converter
480
, a third mixer
490
and a power amplifier
492
.
The mixers
435
,
465
are all for demodulation while the mixer
490
is for modulation. The mixer
435
is for a selected RF frequency and the mixer
465
is for an intermediate frequency (IF). The PLL
1
430
generates clock signals at a high frequency or the RF frequency, the PLL
2
460
generates clock signals having a low frequency or the intermediate frequency (IF).
Transmission data are multiplied with the clock signals having the high frequency from the PLL
430
to have an original transmission data frequency by the mixer
490
. The output signals of the mixer
490
are amplified with a gain at the power amplifier
492
and then radiated through the antenna
405
for transmission.
Operations of the related art super-heterodyne receiver will now be described. Initially, an RF signal is received by the antenna
4

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