Single-chip chipset with integrated graphics controller

Details Single-chip chipset with integrated graphics controller Single-chip chipset with integrated graphics controller

1998-06-11

2001-05-15

Tung, Kee M. (Department: 2671)

Computer graphics processing and selective visual display system

Computer graphic processing system

Integrated circuit

C345S520000, C345S519000, C345S520000, C710S120000

Reexamination Certificate

active

06232990

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to personal computers, and more specifically to a single-chip chipset with integrated graphics controller.
BACKGROUND OF THE INVENTION
Modern personal computers generally comprise a graphics controller that controls the display of data, and which uses a frame buffer memory. This frame buffer is typically a 1 MB memory linked to the graphics controller through a 32 bit bus. When a 2 MB memory is used, a 64 bit bus is used. Computers also comprise system memory used by the processor for running the operating system and applications. This memory is usually accessed through a 64 bit bus.
UMA or Unified Memory Architecture is an architecture where the frame buffer memory space used by the graphics controller is actually part of the system memory. The advantages of such an architecture are the following. First, UMA permits reduction of the overall amount of memory necessary for a computer. Instead of having 16 MB of system memory and 1 MB of frame buffer, a computer only needs 16 MB shared between the system memory and the frame buffer. Second, UMA allows the graphics controller to use a 64 bit bus, even with only 1 MB of frame buffer.
The drawbacks of UMA are the poor performance, due to memory sharing and memory access collision between the graphics controller and the processor, and the fact that less system memory is available for the operating system.
Taking advantage of the improvement of silicon technology, it has been proposed to integrate the graphics controller into a single-chip chipset. The graphics controller thus has direct access to the processor bus. This provides a wider bus for the graphics controller, even with only 1 MB of frame buffer.
FIG. 1
is a schematic view of an embodiment of such a UMA single-chip chipset of the prior art, with its related components. In
FIG. 1
, the single-chip chipset
1
comprises a peripheral bus controller
3
, a memory controller
4
, and a graphics controller
5
. The chipset
1
is connected to a processor
6
through a processor bus
7
, e. g. a 64 bit bus running at 66 MHz. It is also connected to a peripheral bus
8
through the peripheral bus controller
3
. The peripheral bus is typically a bus of the PCI type. The chipset
1
is finally connected to the system memory
9
, through a system bus
10
, e.g. a 64 bit bus at 66 MHz.
As shown by arrows in
FIG. 1
, the graphics controller
5
has access to the system memory
9
, through the memory controller
3
and the system bus
10
. Part of the system memory, as explained above, is used as frame buffer. Such a UMA single-chip chipset is sold by . . . under the reference . . .
Such integration of the memory controller on the chipset gives a clear performance advantage, since the graphics controller sits directly on the processor bus. In the case of a 64 bit bus running at 66 to 100 MHz, this provides access to the graphics controller with a bandwidth of 528 to 800 MB; as a comparison a prior art graphics controller bus like the one provided under the tradename AGP allows a bandwidth of 533 MB. However, the chipset/graphics controller of
FIG. 1
still presents the drawbacks of UMA, as described above.
There also exists a need today for increasingly higher resolution and colour depth, which requires more frame buffer memory, with a high impact on performance. The UMA architecture of
FIG. 1
may provide such features if the size of the system memory is increased, but still presents the same drawbacks.
The object of the invention is to provide an architecture for personal computers, that overcomes the above described drawbacks of UMA, while providing high resolution, colour depth and performance.
Another object of the invention is to provide an easily upgradable architecture, that may easily be adapted to different types of configurations.
SUMMARY OF THE INVENTION
According to the invention, there is provided a single-chip chipset with integrated graphics controller, said chipset including:
a graphics controller;
first external-interface means for connecting to external system memory;
a memory controller connected to said first external-interface means and including means for interfacing the memory controller and graphics controller to allow the latter to access said system memory through said first externalinterface means;
second external-interface means for connecting to an external frame buffer memory;
a frame-buffer controller connected to said second external-interface means and including means for interfacing the frame-buffer controller and graphics controller to allow the latter to access said external frame buffer through said second external-interface means; and
control means for controlling the operative interconnection of the graphics controller with at least the external frame buffer memory through the framebuffer controller.
With this arrangement, the frame buffer may be provided either as part of the system memory or by a separate external memory, as appropriate.
Providing sufficient connectivity on a single chip for two external memories presents its own difficulties. Prefereably, therefore, the frame buffer controller and second external-interface means are designed to provide a high-speed narrow access path to the external frame buffer, thereby minimising the pin count associated with this path whilst giving good performance.
The control means can simply control the connection of the graphics control in response to an external input. Preferably, however, the control means includes detection means for detecting whether an external frame buffer is connected to the second external-interface means. In this case, in one embodiment the control means is responsive to the detection means indicating the presence of an external frame buffer memory, to permit access between the graphics controller and the frame-buffer memory, and otherwise to inhibit such access; access from the graphics controller to the system memory being permitted independently of the whether the frame buffer memory is present. In another embodiment where the control means also controls access of the graphics controller to the system memory through the memory controller, the control means is responsive to the detection means to permit access between the graphics controller and one only of the system memory and frame buffer memory, the control means being responsive to the detection means indicating the presence of an external frame buffer memory, to permit access between the graphics controller and the frame-buffer memory, and otherwise to permit access between the graphics controller and system memory.
The invention further provides a computer having such a single-chip chipset with integrated graphics controller. The computer will be provided with means for receiving a frame buffer memory and means interconnecting said means for receiving to said second external-interface means of the single-chip chipset. The computer can be initially used without a frame buffer being present and later upgraded.
The invention further provides a process for allocating memory to a graphics controller integrated into a single-chip chipset, the process comprising the steps of:
allowing access of the graphics controller to the system memory, through the memory controller, and
allowing access of the graphics controller to the frame buffer through the frame buffer controller when a frame buffer is connected to the second means.


REFERENCES:
patent: 5335322 (1994-08-01), Mattison
patent: 5659715 (1997-08-01), Wu et al.
patent: 5797028 (1998-08-01), Gulick et al.
patent: WO 9515528 (1995-06-01), None
Bursky, D., “Controller Cuts Cost of PC Workstation Graphics”, Electronic Design, vol. 43, No. 13, Jun. 1995.
“Unified Memory Architecture Cuts PC Cost” by Yong Yao, Microprocessor Report, vol. 9, No. 8, pp. 1-5, Jun. 19, 1995.*
RAMBUS-Architectural Overview, pp. 18-23,1993.

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