Single channel serial data receiver

Details Single channel serial data receiver Single channel serial data receiver

1991-03-05

1992-12-15

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

307269, 307601, H04L 7033

Patent

active

051723972

ABSTRACT:
A data latch circuit, a gated clock circuit and a delay line circuit for receiving and decoding combined serial data and clock information are disclosed. The data latch circuit, by eliminating the need to use a clear signal, has no "blind spot" with regards to incoming data and can therefore accept data at a faster rate than known circuits. The gated clock also does not utilize the clear signal of the known art and can therefore produce a higher frequency clock pulse. The delay line prevents pulse compression and pulse collapse by means of a flip-flop and exclusive OR means. The circuits may be used together in a receiver for receiving combined serial data and clock information.

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patent: 5056114 (1991-10-01), Wight
patent: 5058140 (1991-10-01), Johnson

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