Single channel FIR filter architecture to perform combined/paral

Details Single channel FIR filter architecture to perform combined/paral Single channel FIR filter architecture to perform combined/paral

1996-10-08

1998-03-17

Chin, Stephen

Pulse or digital communications

Systems using alternating or pulsating current

Plural channels for transmission of a single pulse train

375235, 375350, 36472416, H04L 512

Patent

active

057295743

ABSTRACT:
A reduced hardware complexity, reduced computational intensity finite impulse response filter architecture for filtering multiple (quadrature) channels of an RF modem comprises a cascaded arrangement of L data register stages through which respective digitally encoded data sample values of a signal to be filtered are sequentially clocked. Each data register stage has a data capacity greater than twice the code width of a respective digitized channel sample, so that each register stage can store both I and Q channel data. A multiplier unit is coupled to the data register and multiplies both I and Q contents of respective ones of the register stages by respective impulse response coefficient values. The resulting I and Q products are summed into I and Q channel convolutional sums.

REFERENCES:
patent: 5222035 (1993-06-01), Nakase et al.
patent: 5515402 (1996-05-01), Chester

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