Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2001-03-23
2002-08-13
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S264000
Reexamination Certificate
active
06433637
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an operational amplifier that operates at low power-supply voltages. In particular, the present invention relates to a method and apparatus that includes a rail-to-rail input trans-conductance stage that supplies a current output to an output trans-conductance stage. The input and output stages operate over the full power supply range.
BACKGROUND OF THE INVENTION
Differential amplifiers normal only operate over a limited range of input voltages. The maximum input voltage range for which a circuit continues to operate as an amplifier is termed the input common-mode range (CMR). When the input voltages (or common mode voltage) exceed the input CMR, transistors become cutoff, saturated, or breakdown in one or more gain stages of the amplifier. Typically, the CMR permits the common mode voltage (V
CM
) to approach within a few volts of either power supply voltage before the amplifier performance is degraded.
A simple differential amplifier (
500
) is shown in FIG.
5
. As shown in the figure, a current source (IDIFF) sources a current into node
501
. Transistor M
51
has a source connected to node
501
, a gate connected to an inverting input terminal (INN), and a drain connected to node
503
. Transistor M
52
has a source connected to node
501
, a gate connected to a non-inverting input terminal (INP), and a drain connected to node
504
. Transistor M
53
is a diode-connected transistor with a gate and drain connected to node
503
, and a source connected to VSS. Transistor M
54
has a gate connected to node
503
, a drain connected to node
504
, and a source connected to VSS. Transistor M
55
has a gate connected to node
504
, a drain connected to an output terminal (VOUT), and a source connected to VSS. A second current source (IOUT) sources a current into the drain of transistor M
55
(V
OUT
). A capacitor (CC) is connected between VOUT and node
103
.
Transistors M
51
and M
52
are a matched pair of PMOS transistors that form a differential input stage of the differential amplifier (
500
). Transistors M
53
and M
54
form an NMOS current mirror, acting as a load for the differential input pair (M
51
, M
52
). Current source IDIFF supplies a “tail current” to bias the differential input pair transistors into their active region of operation. NMOS transistor M
55
serves as an amplifier, with an input at node
504
and an output at VOUT. The capacitor (CC) reduces the gain of the amplifier at high frequencies to provide a stable amplifier by Miller compensation.
The input differential pair transistors (M
51
, M
52
) limit the CMR of differential amplifier
500
. Transistors M
51
and M
52
must be biased in saturation for the amplifier to function properly. A typical threshold voltage of a PMOS transistor (V
TP
) is on the order of −1V. To remain in saturation, the source-to-gate voltage (V
SG
) of transistors M
51
and M
52
must be biased active (V
SG
≧|V
TP
|) Since the input differential pair transistors will be cutoff when V
CM
(the DC level at INM and INP) approaches the V
DD
power supply, the input differential pair transistors will operate as an amplifier when: V
G51
(max)=V
G52
(max)=V
CM
(max)≦V
DD
−|V
TP
|. The active load transistors (M
53
, M
54
), together with the input differential pair transistors (M
51
, M
52
) determine the minimum V
CM
for which the amplifier will operate properly. Transistors M
51
and M
52
must also have a source-to-drain voltage (V
SD
) that exceeds the saturation voltage (V
SD
≧V
SG
−|V
TP
|). The typical threshold voltage of a NMOS transistor (V
TN
) is on the order of +1V. The load transistors M
53
, M
54
must be biased active (V
GS53
=V
GS54
>V
TN
). The minimum V
CM
for amplifier
500
, is determined by: V
G51
(min)=V
G52
(min)=V
CM
(min)≧V
SS
+V
TN
−|V
TP
|. Thus, amplifier
500
does not operate as a rail-to-rail amplifier.
The open loop gain of the amplifier (Av) is determined by the transconductance of transistors M
52
and M
55
. The open loop gain of the amplifier (
500
) is on the order of 60 dB. The capacitor (CC) creates a dominant pole in the amplifier (
500
) such that the gain of the amplifier is reduced at high frequency. The unity-gain bandwidth (GBW) of the amplifier (
500
) is defined as the frequency where the gain drops from the open loop gain down to 0 dB. Since C
C
creates a dominant pole in the amplifier, the unity gain bandwidth (GBW) is proportional to g
m
/C
C
, where g
m
is the trans-conductance of the amplifier.
SUMMARY OF THE INVENTION
In accordance with the invention, the above and other problems are solved by an apparatus and method that is directed to an amplifier with a rail-to-rail output swing that operates on a very low power supply voltage.
Briefly stated, the present invention relates to a method and apparatus that is directed to a rail-to-rail MOS amplifier that operates with a very low power supply. An input stage amplifier operates over rail-to-rail common-mode voltages. The input stage amplifier includes two differential input stages that steer current to loads in a class AB turnaround stage. The class AB turnaround stage converts the differential signals into a single signal that is driven into an output stage amplifier. The output stage amplifier includes level shifting buffer amplifiers that are arranged to bias a pair of MOS output transistors. Each level shifting buffer amplifier is arranged to bias a MOS transistor in a sub-threshold operating region such that the MOS transistor operates as a resistor. The MOS resistor works in conjunction with a MOS diode to provide an AB bias voltage to a gate of a respective one of the output transistors. The level shifting buffer amplifiers are also arranged such that the gate of each output transistor is selectively switched to a power supply voltage, providing maximum gate drive to the output transistor when the output transistor drives a maximum current to an external load. A single capacitor may be employed to provide compensation between the output of the amplifier and the output of the class AB turnaround stage. The sub-threshold operation of the level shifting buffer amplifiers permits the output stage amplifier to operate on power supplies down to roughly a single transistor threshold voltage.
According to a feature of the invention, a rail-to-rail output swing is achieved with a pair of MOS output transistors and a pair of corresponding drive level shifters that bias the output transistors for class AB operation and provide a maximum drive to the output transistors. In one example, the drive level shifters each include a sub-threshold biased MOS transistor operating as a resistive device that is used to generate an AB bias to one of the MOS output transistors.
According to another feature of the invention, drive level shifters in an output stage amplifier drive the gates of MOS output transistors over a maximum swing level such that maximum output current is available to an external load. In one example, the drive level shifters provide maximum gate drive to the MOS output transistors by coupling the gate to one of the power supply voltages.
According to still another feature of the invention, a single compensation capacitor provides high frequency compensation to an output stage amplifier that has a rail-to-rail output swing.
An embodiment of the invention is directed to an apparatus, operating from a high power supply having a high potential and a low power supply having a low potential, that is arranged to provide a rail-to-rail output signal at an output node in response to an input signal at an input node. The apparatus includes a first active load device, that operates as a sub-threshold device, is coupled to the high power supply and a first intermediary node. A first diode device is coupled between the first intermediary node and a first drive node, wherein the first diode device is arranged to provide a high drive signal at t
Hertzberg Brett A.
Merchant & Gould P.C.
National Semiconductor Corporation
Nguyen Khanh Van
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