Single bonding shelf, multi-row wire-bond finger layout for inte

Details Single bonding shelf, multi-row wire-bond finger layout for inte Single bonding shelf, multi-row wire-bond finger layout for inte

1986-04-04

1989-12-26

Macon, Robert S.

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific current responsive fault sensor

361394, 361401, 361414, 174 524, H04N 916

Patent

active

048901539

ABSTRACT:
An integrated circuit assembly (10) includes a bipolar VLSI die (12) contained in a multilayer ceramic pin-grid array package (14). A bonding shelf (18) defined on a single ceramic layer contains an inner row (20) of bonding pads (26) and an outer row (22) of bonding pads (28). Bonding wires (30, 32) extend from bonding pads (34) on the die to the opposing pads on the inner and outer rows to provide an electrical interface between the die and the package. The inner and outer bonding pads are connected by metallized fingers to conductive pads (61, 65) which provide a power and signal interface with an incorporating system.
The inner pads include metallized vias (24) to metallized segments on a layer other than that on which the bonding shelf is defined. Thus, the metallized fingers including the inner row of pads can extend to the pins while passing above or below, rather than between, adjacent pads of the outer row. In this way, the pitch of the package bonding pads is effectively doubled without the misalignment, and resulting problems with shorted bonding wires, inherent when the rows are located on separated bonding shelves.

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