Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-11-14
2006-11-14
Zarabian, Amir (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030, C365S185050, C365S185270, C365S072000
Reexamination Certificate
active
07136306
ABSTRACT:
A method for programming a single bit nonvolatile memory cell integrated on a metal-dielectric-semiconductor technology chip. The memory cell comprises a semiconductor substrate including a source, a drain, and a channel in-between the source and the drain. The memory cell further comprises a control gate that comprises a gate electrode and a dielectric stack. The gate electrode is separated from the channel by the dielectric stack. Further, the dielectric stack comprises at least one charge storage dielectric layer. The method for programming the memory cell comprises applying electrical ground to the source, applying a first voltage having a first polarity to the drain, applying a second voltage of the first polarity to the control gate; and applying a third voltage having a second polarity opposite to the first polarity to the semiconductor substrate.
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Houdt Jan Van
Xue Gang
Interuniversitair Microelektronica Centrum (IMEC)
Pham Ly Duy
Zarabian Amir
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